1 /*
2  * Copyright (c) 2024 Huawei Device Co., Ltd.
3  * Licensed under the Apache License, Version 2.0 (the "License");
4  * you may not use this file except in compliance with the License.
5  * You may obtain a copy of the License at
6  *
7  *     http://www.apache.org/licenses/LICENSE-2.0
8  *
9  * Unless required by applicable law or agreed to in writing, software
10  * distributed under the License is distributed on an "AS IS" BASIS,
11  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12  * See the License for the specific language governing permissions and
13  * limitations under the License.
14  */
15 
16 #ifndef API_RENDER_DEVICE_PIPELINE_STATE_DESC_H
17 #define API_RENDER_DEVICE_PIPELINE_STATE_DESC_H
18 
19 #include <cstdint>
20 
21 #include <base/containers/array_view.h>
22 #include <base/util/formats.h>
23 #include <render/namespace.h>
24 #include <render/resource_handle.h>
25 
26 RENDER_BEGIN_NAMESPACE()
27 /** \addtogroup group_render_pipelinestatedesc
28  *  @{
29  */
30 /** Size 2D */
31 struct Size2D {
32     /** Width */
33     uint32_t width { 0 };
34     /** Height */
35     uint32_t height { 0 };
36 };
37 
38 /** Size 3D */
39 struct Size3D {
40     /** Width */
41     uint32_t width { 0 };
42     /** Height */
43     uint32_t height { 0 };
44     /** Depth */
45     uint32_t depth { 0 };
46 };
47 
48 /** Offset 3D */
49 struct Offset3D {
50     /** X offset */
51     int32_t x { 0 };
52     /** Y offset */
53     int32_t y { 0 };
54     /** Z offset */
55     int32_t z { 0 };
56 };
57 
58 /** Surface transform flag bits */
59 enum SurfaceTransformFlagBits {
60     /** Identity bit */
61     CORE_SURFACE_TRANSFORM_IDENTITY_BIT = 0x00000001,
62     /** Rotate 90 bit */
63     CORE_SURFACE_TRANSFORM_ROTATE_90_BIT = 0x00000002,
64     /** Rotate 180 bit */
65     CORE_SURFACE_TRANSFORM_ROTATE_180_BIT = 0x00000004,
66     /** Rotate 270 bit */
67     CORE_SURFACE_TRANSFORM_ROTATE_270_BIT = 0x00000008,
68 };
69 /** Container for surface transform flag bits */
70 using SurfaceTransformFlags = uint32_t;
71 
72 /** Index type */
73 enum IndexType {
74     /** UINT16 */
75     CORE_INDEX_TYPE_UINT16 = 0,
76     /** UINT32 */
77     CORE_INDEX_TYPE_UINT32 = 1,
78 };
79 
80 /** Memory property flag bits */
81 enum MemoryPropertyFlagBits {
82     /** Device local bit */
83     CORE_MEMORY_PROPERTY_DEVICE_LOCAL_BIT = 0x00000001,
84     /** Host visible bit */
85     CORE_MEMORY_PROPERTY_HOST_VISIBLE_BIT = 0x00000002,
86     /** Host visible bit */
87     CORE_MEMORY_PROPERTY_HOST_COHERENT_BIT = 0x00000004,
88     /** Host cached bit, always preferred not required for allocation */
89     CORE_MEMORY_PROPERTY_HOST_CACHED_BIT = 0x00000008,
90     /** Lazily allocated bit, always preferred not required for allocation */
91     CORE_MEMORY_PROPERTY_LAZILY_ALLOCATED_BIT = 0x00000010,
92     /** Protected bit, always preferred not required for allocation */
93     CORE_MEMORY_PROPERTY_PROTECTED_BIT = 0x00000020,
94 };
95 /** Container for memory property flag bits */
96 using MemoryPropertyFlags = uint32_t;
97 
98 enum FormatFeatureFlagBits {
99     /** Sampled image bit */
100     CORE_FORMAT_FEATURE_SAMPLED_IMAGE_BIT = 0x00000001,
101     /** Storage image bit */
102     CORE_FORMAT_FEATURE_STORAGE_IMAGE_BIT = 0x00000002,
103     /** Image atomic bit */
104     CORE_FORMAT_FEATURE_STORAGE_IMAGE_ATOMIC_BIT = 0x00000004,
105     /** Uniform texel buffer bit */
106     CORE_FORMAT_FEATURE_UNIFORM_TEXEL_BUFFER_BIT = 0x00000008,
107     /** Storage texel buffer bit */
108     CORE_FORMAT_FEATURE_STORAGE_TEXEL_BUFFER_BIT = 0x00000010,
109     /** Storage texel buffer atomic bit */
110     CORE_FORMAT_FEATURE_STORAGE_TEXEL_BUFFER_ATOMIC_BIT = 0x00000020,
111     /** Vertex buffer bit */
112     CORE_FORMAT_FEATURE_VERTEX_BUFFER_BIT = 0x00000040,
113     /** Color attachment bit */
114     CORE_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT = 0x00000080,
115     /** Color attachment blend bit */
116     CORE_FORMAT_FEATURE_COLOR_ATTACHMENT_BLEND_BIT = 0x00000100,
117     /** Depth stencil attachment bit */
118     CORE_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT = 0x00000200,
119     /** Blit src bit */
120     CORE_FORMAT_FEATURE_BLIT_SRC_BIT = 0x00000400,
121     /** Blit dst bit */
122     CORE_FORMAT_FEATURE_BLIT_DST_BIT = 0x00000800,
123     /** Sampled image filter linear bit */
124     CORE_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT = 0x00001000,
125     /** Transfer src bit */
126     CORE_FORMAT_FEATURE_TRANSFER_SRC_BIT = 0x00004000,
127     /** Transfer dst bit */
128     CORE_FORMAT_FEATURE_TRANSFER_DST_BIT = 0x00008000,
129     /** Fragment shading rate attachment bit */
130     CORE_FORMAT_FEATURE_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT = 0x40000000,
131 };
132 /** Format feature flags */
133 using FormatFeatureFlags = uint32_t;
134 
135 /** Format properties */
136 struct FormatProperties {
137     /** Linear tiling feature flags */
138     FormatFeatureFlags linearTilingFeatures { 0u };
139     /** Optimal tiling feature flags */
140     FormatFeatureFlags optimalTilingFeatures { 0u };
141     /** Buffer feature flags */
142     FormatFeatureFlags bufferFeatures { 0u };
143     /** Bytes per pixel */
144     uint32_t bytesPerPixel { 0u };
145 };
146 
147 /** Fragment shading rate properties */
148 struct FragmentShadingRateProperties {
149     /** Min fragment shading rate attachment texel size */
150     Size2D minFragmentShadingRateAttachmentTexelSize;
151     /** Max fragment shading rate attachment texel size */
152     Size2D maxFragmentShadingRateAttachmentTexelSize;
153     /** Max fragment size */
154     Size2D maxFragmentSize;
155 };
156 
157 /** Image layout */
158 enum ImageLayout {
159     /** Undefined */
160     CORE_IMAGE_LAYOUT_UNDEFINED = 0,
161     /** General */
162     CORE_IMAGE_LAYOUT_GENERAL = 1,
163     /** Color attachment optimal */
164     CORE_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL = 2,
165     /** Depth stencil attachment optimal */
166     CORE_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL = 3,
167     /** Depth stencil read only optimal */
168     CORE_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL = 4,
169     /** Shader read only optimal */
170     CORE_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL = 5,
171     /** Transfer source optimal */
172     CORE_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL = 6,
173     /** Transfer destination optimal */
174     CORE_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL = 7,
175     /** Preinitialized */
176     CORE_IMAGE_LAYOUT_PREINITIALIZED = 8,
177     /** Depth read only stencil attachment optimal */
178     CORE_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL = 1000117000,
179     /** Depth attachment stencil read only optimal */
180     CORE_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL = 1000117001,
181     /** Present source */
182     CORE_IMAGE_LAYOUT_PRESENT_SRC = 1000001002,
183     /** Shared present source */
184     CORE_IMAGE_LAYOUT_SHARED_PRESENT = 1000111000,
185     /** Shared present source KHR */
186     CORE_IMAGE_LAYOUT_FRAGMENT_SHADING_RATE_ATTACHMENT_OPTIMAL = 1000164003,
187     /** Max enumeration */
188     CORE_IMAGE_LAYOUT_MAX_ENUM = 0x7FFFFFFF
189 };
190 
191 /** Image aspect flag bits */
192 enum ImageAspectFlagBits {
193     /** Color bit */
194     CORE_IMAGE_ASPECT_COLOR_BIT = 0x00000001,
195     /** Depth bit */
196     CORE_IMAGE_ASPECT_DEPTH_BIT = 0x00000002,
197     /** Stencil bit */
198     CORE_IMAGE_ASPECT_STENCIL_BIT = 0x00000004,
199     /** Metadata bit */
200     CORE_IMAGE_ASPECT_METADATA_BIT = 0x00000008,
201     /** Aspect plane 0 */
202     CORE_IMAGE_ASPECT_PLANE_0_BIT = 0x00000010,
203     /** Aspect plane 1 */
204     CORE_IMAGE_ASPECT_PLANE_1_BIT = 0x00000020,
205     /** Aspect plane 2 */
206     CORE_IMAGE_ASPECT_PLANE_2_BIT = 0x00000040,
207 };
208 /** Container for image aspect flag bits */
209 using ImageAspectFlags = uint32_t;
210 
211 /** Access flag bits */
212 enum AccessFlagBits {
213     /** Indirect command read bit */
214     CORE_ACCESS_INDIRECT_COMMAND_READ_BIT = 0x00000001,
215     /** Index read bit */
216     CORE_ACCESS_INDEX_READ_BIT = 0x00000002,
217     /** Vertex attribute read bit */
218     CORE_ACCESS_VERTEX_ATTRIBUTE_READ_BIT = 0x00000004,
219     /** Uniform read bit */
220     CORE_ACCESS_UNIFORM_READ_BIT = 0x00000008,
221     /** Input attachment read bit */
222     CORE_ACCESS_INPUT_ATTACHMENT_READ_BIT = 0x00000010,
223     /** Shader read bit */
224     CORE_ACCESS_SHADER_READ_BIT = 0x00000020,
225     /** Shader write bit */
226     CORE_ACCESS_SHADER_WRITE_BIT = 0x00000040,
227     /** Color attachment read bit */
228     CORE_ACCESS_COLOR_ATTACHMENT_READ_BIT = 0x00000080,
229     /** Color attachment write bit */
230     CORE_ACCESS_COLOR_ATTACHMENT_WRITE_BIT = 0x00000100,
231     /** Depth stencil attachment read bit */
232     CORE_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT = 0x00000200,
233     /** Depth stencil attachment write bit */
234     CORE_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT = 0x00000400,
235     /** Transfer read bit */
236     CORE_ACCESS_TRANSFER_READ_BIT = 0x00000800,
237     /** Transfer write bit */
238     CORE_ACCESS_TRANSFER_WRITE_BIT = 0x00001000,
239     /** Host read bit */
240     CORE_ACCESS_HOST_READ_BIT = 0x00002000,
241     /** Host write bit */
242     CORE_ACCESS_HOST_WRITE_BIT = 0x00004000,
243     /** Memory read bit */
244     CORE_ACCESS_MEMORY_READ_BIT = 0x00008000,
245     /** Memory write bit */
246     CORE_ACCESS_MEMORY_WRITE_BIT = 0x00010000,
247     /** Fragment shading rate attachment read bit */
248     CORE_ACCESS_FRAGMENT_SHADING_RATE_ATTACHMENT_READ_BIT = 0x00800000,
249 };
250 /** Container for access flag bits */
251 using AccessFlags = uint32_t;
252 
253 /** Pipeline stage flag bits */
254 enum PipelineStageFlagBits {
255     /** Top of pipe bit */
256     CORE_PIPELINE_STAGE_TOP_OF_PIPE_BIT = 0x00000001,
257     /** Draw indirect bit */
258     CORE_PIPELINE_STAGE_DRAW_INDIRECT_BIT = 0x00000002,
259     /** Vertex input bit */
260     CORE_PIPELINE_STAGE_VERTEX_INPUT_BIT = 0x00000004,
261     /** Vertex shader bit */
262     CORE_PIPELINE_STAGE_VERTEX_SHADER_BIT = 0x00000008,
263     /** Fragment shader bit */
264     CORE_PIPELINE_STAGE_FRAGMENT_SHADER_BIT = 0x00000080,
265     /** Early fragment tests bit */
266     CORE_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT = 0x00000100,
267     /** Late fragment tests bit */
268     CORE_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT = 0x00000200,
269     /** Color attachment output bit */
270     CORE_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT = 0x00000400,
271     /** Compute shader bit */
272     CORE_PIPELINE_STAGE_COMPUTE_SHADER_BIT = 0x00000800,
273     /** Transfer bit */
274     CORE_PIPELINE_STAGE_TRANSFER_BIT = 0x00001000,
275     /** Bottom of pipe bit */
276     CORE_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT = 0x00002000,
277     /** Host bit */
278     CORE_PIPELINE_STAGE_HOST_BIT = 0x00004000,
279     /** All graphics bit */
280     CORE_PIPELINE_STAGE_ALL_GRAPHICS_BIT = 0x00008000,
281     /** All commands bit */
282     CORE_PIPELINE_STAGE_ALL_COMMANDS_BIT = 0x00010000,
283     /** Fragment shading rate attacchment bit */
284     CORE_PIPELINE_STAGE_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT = 0x00400000,
285 };
286 /** Container for pipeline stage flag bits */
287 using PipelineStageFlags = uint32_t;
288 
289 /** GPU queue */
290 struct GpuQueue {
291     /** Queue type */
292     enum class QueueType {
293         /** Undefined queue type */
294         UNDEFINED = 0x0,
295         /** Graphics */
296         GRAPHICS = 0x1,
297         /** Compute */
298         COMPUTE = 0x2,
299         /** Transfer */
300         TRANSFER = 0x4,
301     };
302 
303     /** Type of queue */
304     QueueType type { QueueType::UNDEFINED };
305     /** Index of queue */
306     uint32_t index { 0 };
307 };
308 
309 /** Descriptor type */
310 enum DescriptorType {
311     /** Sampler */
312     CORE_DESCRIPTOR_TYPE_SAMPLER = 0,
313     /** Combined image sampler */
314     CORE_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER = 1,
315     /** Sampled image */
316     CORE_DESCRIPTOR_TYPE_SAMPLED_IMAGE = 2,
317     /** Storage image */
318     CORE_DESCRIPTOR_TYPE_STORAGE_IMAGE = 3,
319     /** Uniform texel buffer */
320     CORE_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER = 4,
321     /** Storage texel buffer */
322     CORE_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER = 5,
323     /** Uniform buffer */
324     CORE_DESCRIPTOR_TYPE_UNIFORM_BUFFER = 6,
325     /** Storage buffer */
326     CORE_DESCRIPTOR_TYPE_STORAGE_BUFFER = 7,
327     /** Dynamic uniform buffer */
328     CORE_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC = 8,
329     /** Dynamic storage buffer */
330     CORE_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC = 9,
331     /** Input attachment */
332     CORE_DESCRIPTOR_TYPE_INPUT_ATTACHMENT = 10,
333     /** Acceleration structure */
334     CORE_DESCRIPTOR_TYPE_ACCELERATION_STRUCTURE = 1000150000,
335     /** Max enumeration */
336     CORE_DESCRIPTOR_TYPE_MAX_ENUM = 0x7FFFFFFF
337 };
338 
339 /** Additional descriptor flag bits */
340 enum AdditionalDescriptorFlagBits {
341     /** Immutable sampler is used */
342     CORE_ADDITIONAL_DESCRIPTOR_IMMUTABLE_SAMPLER_BIT = 0x00000001,
343 };
344 /** Container for sampler descriptor flag bits */
345 using AdditionalDescriptorFlags = uint32_t;
346 
347 /** Shader stage flag bits */
348 enum ShaderStageFlagBits {
349     /** Vertex bit */
350     CORE_SHADER_STAGE_VERTEX_BIT = 0x00000001,
351     /** Fragment bit */
352     CORE_SHADER_STAGE_FRAGMENT_BIT = 0x00000010,
353     /** Compute bit */
354     CORE_SHADER_STAGE_COMPUTE_BIT = 0x00000020,
355     /** All graphics */
356     CORE_SHADER_STAGE_ALL_GRAPHICS = 0x0000001F,
357     /** All */
358     CORE_SHADER_STAGE_ALL = 0x7FFFFFFF,
359 };
360 /** Shader stage flags */
361 using ShaderStageFlags = uint32_t;
362 
363 /** Pipeline bind point */
364 enum PipelineBindPoint {
365     /** Bind point graphics */
366     CORE_PIPELINE_BIND_POINT_GRAPHICS = 0,
367     /** Bind point compute */
368     CORE_PIPELINE_BIND_POINT_COMPUTE = 1,
369     /** Max enumeration */
370     CORE_PIPELINE_BIND_POINT_MAX_ENUM = 0x7FFFFFFF
371 };
372 
373 /** Query pipeline statistic flag bits */
374 enum QueryPipelineStatisticFlagBits {
375     /** Input assembly vertices bit */
376     CORE_QUERY_PIPELINE_STATISTIC_INPUT_ASSEMBLY_VERTICES_BIT = 0x00000001,
377     /** Input assembly primitives bit */
378     CORE_QUERY_PIPELINE_STATISTIC_INPUT_ASSEMBLY_PRIMITIVES_BIT = 0x00000002,
379     /** Vertex shader invocations bit */
380     CORE_QUERY_PIPELINE_STATISTIC_VERTEX_SHADER_INVOCATIONS_BIT = 0x00000004,
381     /* Geometry shader invocations bit */
382     CORE_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_INVOCATIONS_BIT = 0x00000008,
383     /* Geometry shader primitives bit */
384     CORE_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT = 0x00000010,
385     /** Clipping invocations bit */
386     CORE_QUERY_PIPELINE_STATISTIC_CLIPPING_INVOCATIONS_BIT = 0x00000020,
387     /** Clipping primitives bit */
388     CORE_QUERY_PIPELINE_STATISTIC_CLIPPING_PRIMITIVES_BIT = 0x00000040,
389     /** Fragment shader invocations bit */
390     CORE_QUERY_PIPELINE_STATISTIC_FRAGMENT_SHADER_INVOCATIONS_BIT = 0x00000080,
391     /* Tesselation control shader patches bit */
392     CORE_QUERY_PIPELINE_STATISTIC_TESSELLATION_CONTROL_SHADER_PATCHES_BIT = 0x00000100,
393     /* Tesselation evaluation shader invocations bit */
394     CORE_QUERY_PIPELINE_STATISTIC_TESSELLATION_EVALUATION_SHADER_INVOCATIONS_BIT = 0x00000200,
395     /** Compute shader invocations bit */
396     CORE_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT = 0x00000400,
397 };
398 /** Query pipeline statistic flags */
399 using QueryPipelineStatisticFlags = uint32_t;
400 
401 /** Query type */
402 enum QueryType {
403     /** Timestamp */
404     CORE_QUERY_TYPE_TIMESTAMP = 2,
405     /** Max enumeration */
406     CORE_QUERY_TYPE_MAX_ENUM = 0x7FFFFFFF
407 };
408 
409 /** Vertex input rate */
410 enum VertexInputRate {
411     /** Vertex */
412     CORE_VERTEX_INPUT_RATE_VERTEX = 0,
413     /** Instance */
414     CORE_VERTEX_INPUT_RATE_INSTANCE = 1,
415 };
416 
417 /** Polygon mode */
418 enum PolygonMode {
419     /** Fill */
420     CORE_POLYGON_MODE_FILL = 0,
421     /** Line */
422     CORE_POLYGON_MODE_LINE = 1,
423     /** Point */
424     CORE_POLYGON_MODE_POINT = 2,
425 };
426 
427 /** Cull mode flag bits */
428 enum CullModeFlagBits {
429     /** None */
430     CORE_CULL_MODE_NONE = 0,
431     /** Front bit */
432     CORE_CULL_MODE_FRONT_BIT = 0x00000001,
433     /** Back bit */
434     CORE_CULL_MODE_BACK_BIT = 0x00000002,
435     /** Front and back bit */
436     CORE_CULL_MODE_FRONT_AND_BACK = 0x00000003,
437 };
438 /** Cull mode flags */
439 using CullModeFlags = uint32_t;
440 
441 /** Front face */
442 enum FrontFace {
443     /** Counter clockwise */
444     CORE_FRONT_FACE_COUNTER_CLOCKWISE = 0,
445     /** Clockwise */
446     CORE_FRONT_FACE_CLOCKWISE = 1,
447 };
448 
449 /** Stencil face flag bits */
450 enum StencilFaceFlagBits {
451     /** Face front bit */
452     CORE_STENCIL_FACE_FRONT_BIT = 0x00000001,
453     /** Face back bit */
454     CORE_STENCIL_FACE_BACK_BIT = 0x00000002,
455     /** Front and back */
456     CORE_STENCIL_FRONT_AND_BACK = 0x00000003,
457 };
458 /** Lume stencil face flags */
459 using StencilFaceFlags = uint32_t;
460 
461 /** Compare op */
462 enum CompareOp {
463     /** Never */
464     CORE_COMPARE_OP_NEVER = 0,
465     /** Less */
466     CORE_COMPARE_OP_LESS = 1,
467     /** Equal */
468     CORE_COMPARE_OP_EQUAL = 2,
469     /** Less or equal */
470     CORE_COMPARE_OP_LESS_OR_EQUAL = 3,
471     /** Greater */
472     CORE_COMPARE_OP_GREATER = 4,
473     /** Not equal */
474     CORE_COMPARE_OP_NOT_EQUAL = 5,
475     /** Greater or equal */
476     CORE_COMPARE_OP_GREATER_OR_EQUAL = 6,
477     /** Always */
478     CORE_COMPARE_OP_ALWAYS = 7,
479 };
480 
481 /** Stencil op */
482 enum StencilOp {
483     /** Keep */
484     CORE_STENCIL_OP_KEEP = 0,
485     /** Zero */
486     CORE_STENCIL_OP_ZERO = 1,
487     /** Replace */
488     CORE_STENCIL_OP_REPLACE = 2,
489     /** Increment and clamp */
490     CORE_STENCIL_OP_INCREMENT_AND_CLAMP = 3,
491     /** Decrement and clamp */
492     CORE_STENCIL_OP_DECREMENT_AND_CLAMP = 4,
493     /** Invert */
494     CORE_STENCIL_OP_INVERT = 5,
495     /** Increment and wrap */
496     CORE_STENCIL_OP_INCREMENT_AND_WRAP = 6,
497     /** Decrement and wrap */
498     CORE_STENCIL_OP_DECREMENT_AND_WRAP = 7,
499 };
500 
501 /** Primitive topology */
502 enum PrimitiveTopology {
503     /** Point list */
504     CORE_PRIMITIVE_TOPOLOGY_POINT_LIST = 0,
505     /** Line list */
506     CORE_PRIMITIVE_TOPOLOGY_LINE_LIST = 1,
507     /** Line strip */
508     CORE_PRIMITIVE_TOPOLOGY_LINE_STRIP = 2,
509     /** Triangle list */
510     CORE_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST = 3,
511     /** Triangle strip */
512     CORE_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP = 4,
513     /** Triangle fan */
514     CORE_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN = 5,
515     /** Line list with adjacency */
516     CORE_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY = 6,
517     /** Line strip with adjacency */
518     CORE_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY = 7,
519     /** Triangle list with adjacency */
520     CORE_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY = 8,
521     /** Triangle strip with adjacency */
522     CORE_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY = 9,
523     /** Patch list */
524     CORE_PRIMITIVE_TOPOLOGY_PATCH_LIST = 10,
525 };
526 
527 /** Blend factor */
528 enum BlendFactor {
529     /** Zero */
530     CORE_BLEND_FACTOR_ZERO = 0,
531     /** One */
532     CORE_BLEND_FACTOR_ONE = 1,
533     /** Source color */
534     CORE_BLEND_FACTOR_SRC_COLOR = 2,
535     /** One minus source color */
536     CORE_BLEND_FACTOR_ONE_MINUS_SRC_COLOR = 3,
537     /** Destination color */
538     CORE_BLEND_FACTOR_DST_COLOR = 4,
539     /** One minus destination color */
540     CORE_BLEND_FACTOR_ONE_MINUS_DST_COLOR = 5,
541     /** Source alpha */
542     CORE_BLEND_FACTOR_SRC_ALPHA = 6,
543     /** One minus source alpha */
544     CORE_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA = 7,
545     /** Destination alpha */
546     CORE_BLEND_FACTOR_DST_ALPHA = 8,
547     /** One minus destination alpha */
548     CORE_BLEND_FACTOR_ONE_MINUS_DST_ALPHA = 9,
549     /** Constant color */
550     CORE_BLEND_FACTOR_CONSTANT_COLOR = 10,
551     /** One minus constant color */
552     CORE_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR = 11,
553     /** Constant alpha */
554     CORE_BLEND_FACTOR_CONSTANT_ALPHA = 12,
555     /** One minus constant alpha */
556     CORE_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA = 13,
557     /** Source alpha saturate */
558     CORE_BLEND_FACTOR_SRC_ALPHA_SATURATE = 14,
559     /** Source one color */
560     CORE_BLEND_FACTOR_SRC1_COLOR = 15,
561     /** One minus source one color */
562     CORE_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR = 16,
563     /** Source one alpha */
564     CORE_BLEND_FACTOR_SRC1_ALPHA = 17,
565     /** One minus source one alpha */
566     CORE_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA = 18,
567 };
568 
569 /** Blend op */
570 enum BlendOp {
571     /** Add */
572     CORE_BLEND_OP_ADD = 0,
573     /** Subtract */
574     CORE_BLEND_OP_SUBTRACT = 1,
575     /** Reverse subtract */
576     CORE_BLEND_OP_REVERSE_SUBTRACT = 2,
577     /** Min */
578     CORE_BLEND_OP_MIN = 3,
579     /** Max */
580     CORE_BLEND_OP_MAX = 4,
581 };
582 
583 /** Color component flag bits */
584 enum ColorComponentFlagBits {
585     /** Red bit */
586     CORE_COLOR_COMPONENT_R_BIT = 0x00000001,
587     /** Green bit */
588     CORE_COLOR_COMPONENT_G_BIT = 0x00000002,
589     /** Blue bit */
590     CORE_COLOR_COMPONENT_B_BIT = 0x00000004,
591     /** Alpha bit */
592     CORE_COLOR_COMPONENT_A_BIT = 0x00000008,
593 };
594 /** Color component flags */
595 using ColorComponentFlags = uint32_t;
596 
597 /** Logic op */
598 enum LogicOp {
599     /** Clear */
600     CORE_LOGIC_OP_CLEAR = 0,
601     /** And */
602     CORE_LOGIC_OP_AND = 1,
603     /** And reverse */
604     CORE_LOGIC_OP_AND_REVERSE = 2,
605     /** Copy */
606     CORE_LOGIC_OP_COPY = 3,
607     /** And inverted */
608     CORE_LOGIC_OP_AND_INVERTED = 4,
609     /** No op */
610     CORE_LOGIC_OP_NO_OP = 5,
611     /** Xor */
612     CORE_LOGIC_OP_XOR = 6,
613     /** Or */
614     CORE_LOGIC_OP_OR = 7,
615     /** Nor */
616     CORE_LOGIC_OP_NOR = 8,
617     /** Equivalent */
618     CORE_LOGIC_OP_EQUIVALENT = 9,
619     /** Invert */
620     CORE_LOGIC_OP_INVERT = 10,
621     /** Or reverse */
622     CORE_LOGIC_OP_OR_REVERSE = 11,
623     /** Copy inverted */
624     CORE_LOGIC_OP_COPY_INVERTED = 12,
625     /** Or inverted */
626     CORE_LOGIC_OP_OR_INVERTED = 13,
627     /** Nand */
628     CORE_LOGIC_OP_NAND = 14,
629     /** Set */
630     CORE_LOGIC_OP_SET = 15,
631 };
632 
633 /** Attachment load op */
634 enum AttachmentLoadOp {
635     /** Load */
636     CORE_ATTACHMENT_LOAD_OP_LOAD = 0,
637     /** Clear */
638     CORE_ATTACHMENT_LOAD_OP_CLEAR = 1,
639     /** Dont care */
640     CORE_ATTACHMENT_LOAD_OP_DONT_CARE = 2,
641 };
642 
643 /** Attachment store op */
644 enum AttachmentStoreOp {
645     /** Store */
646     CORE_ATTACHMENT_STORE_OP_STORE = 0,
647     /** Dont care */
648     CORE_ATTACHMENT_STORE_OP_DONT_CARE = 1,
649 };
650 
651 /** Clear color value */
652 union ClearColorValue {
653     ClearColorValue() = default;
654     ~ClearColorValue() = default;
ClearColorValue(float r,float g,float b,float a)655     constexpr ClearColorValue(float r, float g, float b, float a) : float32 { r, g, b, a } {};
ClearColorValue(int32_t r,int32_t g,int32_t b,int32_t a)656     constexpr ClearColorValue(int32_t r, int32_t g, int32_t b, int32_t a) : int32 { r, g, b, a } {};
ClearColorValue(uint32_t r,uint32_t g,uint32_t b,uint32_t a)657     constexpr ClearColorValue(uint32_t r, uint32_t g, uint32_t b, uint32_t a) : uint32 { r, g, b, a } {};
658     /** Float32 array of 4 */
659     float float32[4];
660     /** int32 array of 4 */
661     int32_t int32[4];
662     /** uint32 array of 4 */
663     uint32_t uint32[4];
664 };
665 
666 /** Clear depth stencil value */
667 struct ClearDepthStencilValue {
668     /** Depth, default value 1.0f */
669     float depth;
670     /** Stencil */
671     uint32_t stencil;
672 };
673 
674 /** Clear value */
675 union ClearValue {
676     ClearValue() = default;
677     ~ClearValue() = default;
ClearValue(const ClearColorValue & color)678     constexpr explicit ClearValue(const ClearColorValue& color) : color { color } {};
ClearValue(const ClearDepthStencilValue & depthStencil)679     constexpr explicit ClearValue(const ClearDepthStencilValue& depthStencil) : depthStencil { depthStencil } {};
ClearValue(float r,float g,float b,float a)680     constexpr ClearValue(float r, float g, float b, float a) : color { r, g, b, a } {};
ClearValue(int32_t r,int32_t g,int32_t b,int32_t a)681     constexpr ClearValue(int32_t r, int32_t g, int32_t b, int32_t a) : color { r, g, b, a } {};
ClearValue(uint32_t r,uint32_t g,uint32_t b,uint32_t a)682     constexpr ClearValue(uint32_t r, uint32_t g, uint32_t b, uint32_t a) : color { r, g, b, a } {};
ClearValue(float depth,uint32_t stencil)683     constexpr ClearValue(float depth, uint32_t stencil) : depthStencil { depth, stencil } {};
684 
685     /** Color */
686     ClearColorValue color;
687     /** Depth stencil */
688     ClearDepthStencilValue depthStencil;
689 };
690 
691 /** Dynamic state flag bits
692  * Dynamic state flags only map to basic dynamic states.
693  * Use DynamicStateEnum s when creating the actual pso objects.
694  */
695 enum DynamicStateFlagBits {
696     /** Undefined */
697     CORE_DYNAMIC_STATE_UNDEFINED = 0,
698     /** Viewport */
699     CORE_DYNAMIC_STATE_VIEWPORT = (1 << 0),
700     /** Scissor */
701     CORE_DYNAMIC_STATE_SCISSOR = (1 << 1),
702     /** Line width */
703     CORE_DYNAMIC_STATE_LINE_WIDTH = (1 << 2),
704     /** Depth bias */
705     CORE_DYNAMIC_STATE_DEPTH_BIAS = (1 << 3),
706     /** Blend constants */
707     CORE_DYNAMIC_STATE_BLEND_CONSTANTS = (1 << 4),
708     /** Depth bounds */
709     CORE_DYNAMIC_STATE_DEPTH_BOUNDS = (1 << 5),
710     /** Stencil compare mask */
711     CORE_DYNAMIC_STATE_STENCIL_COMPARE_MASK = (1 << 6),
712     /** Stencil write mask */
713     CORE_DYNAMIC_STATE_STENCIL_WRITE_MASK = (1 << 7),
714     /** Stencil reference */
715     CORE_DYNAMIC_STATE_STENCIL_REFERENCE = (1 << 8),
716 };
717 /** Dynamic state flags */
718 using DynamicStateFlags = uint32_t;
719 
720 /** Dynamic states */
721 enum DynamicStateEnum {
722     /** Viewport */
723     CORE_DYNAMIC_STATE_ENUM_VIEWPORT = 0,
724     /** Scissor */
725     CORE_DYNAMIC_STATE_ENUM_SCISSOR = 1,
726     /** Line width */
727     CORE_DYNAMIC_STATE_ENUM_LINE_WIDTH = 2,
728     /** Depth bias */
729     CORE_DYNAMIC_STATE_ENUM_DEPTH_BIAS = 3,
730     /** Blend constants */
731     CORE_DYNAMIC_STATE_ENUM_BLEND_CONSTANTS = 4,
732     /** Depth bounds */
733     CORE_DYNAMIC_STATE_ENUM_DEPTH_BOUNDS = 5,
734     /** Stencil compare mask */
735     CORE_DYNAMIC_STATE_ENUM_STENCIL_COMPARE_MASK = 6,
736     /** Stencil write mask */
737     CORE_DYNAMIC_STATE_ENUM_STENCIL_WRITE_MASK = 7,
738     /** Stencil reference */
739     CORE_DYNAMIC_STATE_ENUM_STENCIL_REFERENCE = 8,
740     /** Fragment shading rate */
741     CORE_DYNAMIC_STATE_ENUM_FRAGMENT_SHADING_RATE = 1000226000,
742     /** Max enumeration */
743     CORE_DYNAMIC_STATE_ENUM_MAX_ENUM = 0x7FFFFFFF
744 };
745 
746 /** Resolve mode flag bits */
747 enum ResolveModeFlagBits {
748     /** None. No resolve mode done */
749     CORE_RESOLVE_MODE_NONE = 0,
750     /** Resolve value is same as sample zero */
751     CORE_RESOLVE_MODE_SAMPLE_ZERO_BIT = 0x00000001,
752     /** Resolve value is same as average of all samples */
753     CORE_RESOLVE_MODE_AVERAGE_BIT = 0x00000002,
754     /** Resolve value is same as min of all samples */
755     CORE_RESOLVE_MODE_MIN_BIT = 0x00000004,
756     /** Resolve value is same as max of all samples */
757     CORE_RESOLVE_MODE_MAX_BIT = 0x00000008,
758 };
759 /** Resolve mode flags */
760 using ResolveModeFlags = uint32_t;
761 
762 /** SubpassContents Specifies how commands in the first subpass are provided
763  * CORE_SUBPASS_CONTENTS_INLINE == subpasses are recorded to the same render command list
764  * CORE_SUBPASS_CONTENTS_SECONDARY_COMMAND_LISTS == subpasses are recorded to secondary command lists
765  */
766 enum SubpassContents {
767     /** Inline */
768     CORE_SUBPASS_CONTENTS_INLINE = 0,
769     /* Secondary command lists */
770     CORE_SUBPASS_CONTENTS_SECONDARY_COMMAND_LISTS = 1,
771 };
772 
773 /** Fragment shading rate combiner op */
774 enum FragmentShadingRateCombinerOp {
775     /** Keep */
776     CORE_FRAGMENT_SHADING_RATE_COMBINER_OP_KEEP = 0,
777     /** Replace */
778     CORE_FRAGMENT_SHADING_RATE_COMBINER_OP_REPLACE = 1,
779     /** Min */
780     CORE_FRAGMENT_SHADING_RATE_COMBINER_OP_MIN = 2,
781     /** Max */
782     CORE_FRAGMENT_SHADING_RATE_COMBINER_OP_MAX = 3,
783     /** Mul */
784     CORE_FRAGMENT_SHADING_RATE_COMBINER_OP_MUL = 4,
785 };
786 
787 /** Fragment shading rate combiner operations for commands */
788 struct FragmentShadingRateCombinerOps {
789     /** First combiner (combine pipeline and primitive shading rates) */
790     FragmentShadingRateCombinerOp op1 { CORE_FRAGMENT_SHADING_RATE_COMBINER_OP_KEEP };
791     /** Second combiner (combine the first with attachment fragment shading rate) */
792     FragmentShadingRateCombinerOp op2 { CORE_FRAGMENT_SHADING_RATE_COMBINER_OP_KEEP };
793 };
794 
795 /** Pipeline state constants */
796 struct PipelineStateConstants {
797     /** GPU buffer whole size */
798     static constexpr uint32_t GPU_BUFFER_WHOLE_SIZE { ~0u };
799     /** GPU image all mip levels */
800     static constexpr uint32_t GPU_IMAGE_ALL_MIP_LEVELS { ~0u };
801     /** GPU image all layers */
802     static constexpr uint32_t GPU_IMAGE_ALL_LAYERS { ~0u };
803     /** Max vertex buffer count */
804     static constexpr uint32_t MAX_VERTEX_BUFFER_COUNT { 8u };
805 
806     /** Max input attachment count */
807     static constexpr uint32_t MAX_INPUT_ATTACHMENT_COUNT { 8u };
808     /** Max color attachment count */
809     static constexpr uint32_t MAX_COLOR_ATTACHMENT_COUNT { 8u };
810     /** Max resolve attachment count */
811     static constexpr uint32_t MAX_RESOLVE_ATTACHMENT_COUNT { 4u };
812     /** Max render pass attachment count */
813     static constexpr uint32_t MAX_RENDER_PASS_ATTACHMENT_COUNT { 8u };
814     /** Max render node gpu wait signals */
815     static constexpr uint32_t MAX_RENDER_NODE_GPU_WAIT_SIGNALS { 4u };
816 };
817 
818 /** Viewport descriptor
819  * x and y are upper left corner (x,y) */
820 struct ViewportDesc {
821     /** X point */
822     float x { 0.0f };
823     /** Y point */
824     float y { 0.0f };
825     /** Width */
826     float width { 0.0f };
827     /** Height */
828     float height { 0.0f };
829 
830     /** Min depth (0.0f - 1.0f) */
831     float minDepth { 0.0f };
832     /** Max depth (0.0f - 1.0f) */
833     float maxDepth { 1.0f };
834 };
835 
836 /** Scissor descriptor */
837 struct ScissorDesc {
838     /** X offset */
839     int32_t offsetX { 0 };
840     /** Y offset */
841     int32_t offsetY { 0 };
842     /** Extent width */
843     uint32_t extentWidth { 0 };
844     /** Extent height */
845     uint32_t extentHeight { 0 };
846 };
847 
848 /** Image subresource layers */
849 struct ImageSubresourceLayers {
850     /** Image aspect flags */
851     ImageAspectFlags imageAspectFlags { 0 };
852     /** Mip level */
853     uint32_t mipLevel { 0 };
854     /** Base array layer */
855     uint32_t baseArrayLayer { 0 };
856     /** Layer count */
857     uint32_t layerCount { PipelineStateConstants::GPU_IMAGE_ALL_LAYERS };
858 };
859 
860 /** Image subresource range */
861 struct ImageSubresourceRange {
862     /** Image aspect flags */
863     ImageAspectFlags imageAspectFlags { 0 };
864     /** Base mip level */
865     uint32_t baseMipLevel { 0 };
866     /** Level count */
867     uint32_t levelCount { PipelineStateConstants::GPU_IMAGE_ALL_MIP_LEVELS };
868     /** Base array layer */
869     uint32_t baseArrayLayer { 0 };
870     /** Layer count */
871     uint32_t layerCount { PipelineStateConstants::GPU_IMAGE_ALL_LAYERS };
872 };
873 
874 /** Image blit */
875 struct ImageBlit {
876     /** Source subresource */
877     ImageSubresourceLayers srcSubresource;
878     /** Source offsets (top left and bottom right coordinates) */
879     Size3D srcOffsets[2u];
880     /** Destination subresource */
881     ImageSubresourceLayers dstSubresource;
882     /** Destination offsets (top left and bottom right coordinates) */
883     Size3D dstOffsets[2u];
884 };
885 
886 /** Memory barrier with pipeline stages */
887 struct GeneralBarrier {
888     /** Access flags */
889     AccessFlags accessFlags { 0 };
890     /** Pipeline stage flags */
891     PipelineStageFlags pipelineStageFlags { 0 };
892 };
893 
894 /** Buffer resource barrier */
895 struct BufferResourceBarrier {
896     /** Access flags */
897     AccessFlags accessFlags { 0 };
898     /** Pipeline stage flags */
899     PipelineStageFlags pipelineStageFlags { 0 };
900 };
901 
902 /** Image resource barrier */
903 struct ImageResourceBarrier {
904     /** Access flags */
905     AccessFlags accessFlags { 0 };
906     /** Pipeline stage flags */
907     PipelineStageFlags pipelineStageFlags { 0 };
908     /** Image layout */
909     ImageLayout imageLayout { ImageLayout::CORE_IMAGE_LAYOUT_UNDEFINED };
910 };
911 
912 /** Buffer copy */
913 struct BufferCopy {
914     /** Offset to source buffer */
915     uint32_t srcOffset { 0 };
916     /** Offset to destination buffer */
917     uint32_t dstOffset { 0 };
918     /** Size of copy */
919     uint32_t size { 0 };
920 };
921 
922 /** Buffer image copy */
923 struct BufferImageCopy {
924     /** Buffer offset */
925     uint32_t bufferOffset { 0 };
926     /** Buffer row length */
927     uint32_t bufferRowLength { 0 };
928     /** Buffer image height */
929     uint32_t bufferImageHeight { 0 };
930     /** Image subresource */
931     ImageSubresourceLayers imageSubresource;
932     /** Image offset */
933     Size3D imageOffset;
934     /** Image extent */
935     Size3D imageExtent;
936 };
937 
938 /** Image copy */
939 struct ImageCopy {
940     /** Src image subresource */
941     ImageSubresourceLayers srcSubresource;
942     /** Src offset */
943     Offset3D srcOffset;
944     /** Dst image subresource */
945     ImageSubresourceLayers dstSubresource;
946     /** Dst offset */
947     Offset3D dstOffset;
948     /** Texel size of copy */
949     Size3D extent;
950 };
951 
952 /** GPU resource state in pipeline */
953 struct GpuResourceState {
954     /** Shader stage flags */
955     ShaderStageFlags shaderStageFlags { 0 };
956 
957     /** Access flags */
958     AccessFlags accessFlags { 0 };
959     /** Pipeline stage flags */
960     PipelineStageFlags pipelineStageFlags { 0 };
961 
962     /** GPU queue */
963     GpuQueue gpuQueue {};
964 };
965 
966 /** Render pass descriptor */
967 struct RenderPassDesc {
968     /** Render area */
969     struct RenderArea {
970         /** X offset */
971         int32_t offsetX { 0 };
972         /** Y offset */
973         int32_t offsetY { 0 };
974         /** Extent width */
975         uint32_t extentWidth { 0u };
976         /** Extent height */
977         uint32_t extentHeight { 0u };
978     };
979 
980     /** Attachment descriptor */
981     struct AttachmentDesc {
982         /** Layer for layered image */
983         uint32_t layer { 0u };
984         /** Mip level to target on mipped image */
985         uint32_t mipLevel { 0u };
986 
987         // following values are not needed in render pass compatibility
988         /** Load operation */
989         AttachmentLoadOp loadOp { AttachmentLoadOp::CORE_ATTACHMENT_LOAD_OP_DONT_CARE };
990         /** Store operation */
991         AttachmentStoreOp storeOp { AttachmentStoreOp::CORE_ATTACHMENT_STORE_OP_DONT_CARE };
992 
993         /** Stencil load operation */
994         AttachmentLoadOp stencilLoadOp { AttachmentLoadOp::CORE_ATTACHMENT_LOAD_OP_DONT_CARE };
995         /** Stencil store operation */
996         AttachmentStoreOp stencilStoreOp { AttachmentStoreOp::CORE_ATTACHMENT_STORE_OP_DONT_CARE };
997 
998         /** Clear value (union ClearColorValue or ClearDepthStencilValue) */
999         ClearValue clearValue {};
1000     };
1001 
1002     /** Attachment count */
1003     uint32_t attachmentCount { 0u };
1004 
1005     /** Attachment handles */
1006     RenderHandle attachmentHandles[PipelineStateConstants::MAX_RENDER_PASS_ATTACHMENT_COUNT];
1007     /** Attachments */
1008     AttachmentDesc attachments[PipelineStateConstants::MAX_RENDER_PASS_ATTACHMENT_COUNT];
1009 
1010     /** Render area */
1011     RenderArea renderArea;
1012 
1013     /** Subpass count */
1014     uint32_t subpassCount { 0u };
1015     /** Subpass contents */
1016     SubpassContents subpassContents { SubpassContents::CORE_SUBPASS_CONTENTS_INLINE };
1017 };
1018 
1019 /** Render pass descriptor with render handle references */
1020 struct RenderPassDescWithHandleReference {
1021     /** Attachment count */
1022     uint32_t attachmentCount { 0u };
1023 
1024     /** Attachment handles */
1025     RenderHandleReference attachmentHandles[PipelineStateConstants::MAX_RENDER_PASS_ATTACHMENT_COUNT];
1026     /** Attachments */
1027     RenderPassDesc::AttachmentDesc attachments[PipelineStateConstants::MAX_RENDER_PASS_ATTACHMENT_COUNT];
1028 
1029     /** Render area */
1030     RenderPassDesc::RenderArea renderArea;
1031 
1032     /** Subpass count */
1033     uint32_t subpassCount { 0u };
1034     /** Subpass contents */
1035     SubpassContents subpassContents { SubpassContents::CORE_SUBPASS_CONTENTS_INLINE };
1036 };
1037 
1038 /** Render pass subpass descriptor */
1039 struct RenderPassSubpassDesc {
1040     // indices to render pass attachments
1041     /** Depth attachment index */
1042     uint32_t depthAttachmentIndex { ~0u };
1043     /** Depth resolve attachment index */
1044     uint32_t depthResolveAttachmentIndex { ~0u };
1045     /** Input attachment indices */
1046     uint32_t inputAttachmentIndices[PipelineStateConstants::MAX_INPUT_ATTACHMENT_COUNT] {};
1047     /** Color attachment indices */
1048     uint32_t colorAttachmentIndices[PipelineStateConstants::MAX_COLOR_ATTACHMENT_COUNT] {};
1049     /** Resolve attachment indices */
1050     uint32_t resolveAttachmentIndices[PipelineStateConstants::MAX_RESOLVE_ATTACHMENT_COUNT] {};
1051     /** Fragment shading rate attachment index */
1052     uint32_t fragmentShadingRateAttachmentIndex { ~0u };
1053 
1054     // attachment counts in this subpass
1055     /** Depth attachment count in this subpass */
1056     uint32_t depthAttachmentCount { 0u };
1057     /** Depth resolve attachment count in this subpass */
1058     uint32_t depthResolveAttachmentCount { 0u };
1059     /** Input attachment count in this subpass */
1060     uint32_t inputAttachmentCount { 0u };
1061     /** Color attachment count in this subpass */
1062     uint32_t colorAttachmentCount { 0u };
1063     /** Resolve attachment count in this subpass */
1064     uint32_t resolveAttachmentCount { 0u };
1065     /** Fragmend shading rate attachment count in this subpass */
1066     uint32_t fragmentShadingRateAttachmentCount { 0u };
1067 
1068     /** Depth resolve mode flag bit */
1069     ResolveModeFlagBits depthResolveModeFlagBit { ResolveModeFlagBits::CORE_RESOLVE_MODE_NONE };
1070     /** Stencil resolve mode flag bit */
1071     ResolveModeFlagBits stencilResolveModeFlagBit { ResolveModeFlagBits::CORE_RESOLVE_MODE_NONE };
1072 
1073     /** Shading rate texel size for subpass (will be clamped to device limits automatically if not set accordingly) */
1074     Size2D shadingRateTexelSize { 1u, 1u };
1075 
1076     /** Multi-view bitfield of view indices. Multi-view is ignored while zero. */
1077     uint32_t viewMask { 0u };
1078 };
1079 
1080 /** Render pass */
1081 struct RenderPass {
1082     /** Render pass descriptor */
1083     RenderPassDesc renderPassDesc;
1084     /** Subpass start index */
1085     uint32_t subpassStartIndex { 0u };
1086     /** Subpass descriptor */
1087     RenderPassSubpassDesc subpassDesc;
1088 };
1089 
1090 /** Render pass with render handle references */
1091 struct RenderPassWithHandleReference {
1092     /** Render pass descriptor */
1093     RenderPassDescWithHandleReference renderPassDesc;
1094     /** Subpass start index */
1095     uint32_t subpassStartIndex { 0u };
1096     /** Subpass descriptor */
1097     RenderPassSubpassDesc subpassDesc;
1098 };
1099 
1100 /** Forced graphics state flag bits */
1101 enum GraphicsStateFlagBits {
1102     /** Input assembly bit */
1103     CORE_GRAPHICS_STATE_INPUT_ASSEMBLY_BIT = 0x00000001,
1104     /** Rastarization state bit */
1105     CORE_GRAPHICS_STATE_RASTERIZATION_STATE_BIT = 0x00000002,
1106     /** Depth stencil state bit */
1107     CORE_GRAPHICS_STATE_DEPTH_STENCIL_STATE_BIT = 0x00000004,
1108     /** Color blend state bit */
1109     CORE_GRAPHICS_STATE_COLOR_BLEND_STATE_BIT = 0x00000008,
1110 };
1111 /** Container for graphics state flag bits */
1112 using GraphicsStateFlags = uint32_t;
1113 
1114 /** Graphics state */
1115 struct GraphicsState {
1116     /** Stencil operation state */
1117     struct StencilOpState {
1118         /** Fail operation */
1119         StencilOp failOp { StencilOp::CORE_STENCIL_OP_KEEP };
1120         /** Pass operation */
1121         StencilOp passOp { StencilOp::CORE_STENCIL_OP_KEEP };
1122         /** Depth fail operation */
1123         StencilOp depthFailOp { StencilOp::CORE_STENCIL_OP_KEEP };
1124         /** Compare operation */
1125         CompareOp compareOp { CompareOp::CORE_COMPARE_OP_NEVER };
1126         /** Compare mask */
1127         uint32_t compareMask { 0 };
1128         /** Write mask */
1129         uint32_t writeMask { 0 };
1130         /** Reference */
1131         uint32_t reference { 0 };
1132     };
1133 
1134     /** Rasterization state */
1135     struct RasterizationState {
1136         /** Enable depth clamp */
1137         bool enableDepthClamp { false };
1138         /** Enable depth bias */
1139         bool enableDepthBias { false };
1140         /** Enable rasterizer discard */
1141         bool enableRasterizerDiscard { false };
1142 
1143         /** Polygon mode */
1144         PolygonMode polygonMode { PolygonMode::CORE_POLYGON_MODE_FILL };
1145         /** Cull mode flags */
1146         CullModeFlags cullModeFlags { CullModeFlagBits::CORE_CULL_MODE_NONE };
1147         /** Front face */
1148         FrontFace frontFace { FrontFace::CORE_FRONT_FACE_COUNTER_CLOCKWISE };
1149 
1150         /** Depth bias constant factor */
1151         float depthBiasConstantFactor { 0.0f };
1152         /** Depth bias clamp */
1153         float depthBiasClamp { 0.0f };
1154         /** Depth bias slope factor */
1155         float depthBiasSlopeFactor { 0.0f };
1156 
1157         /** Line width */
1158         float lineWidth { 1.0f };
1159     };
1160 
1161     /** Depth stencil state */
1162     struct DepthStencilState {
1163         /** Enable depth test */
1164         bool enableDepthTest { false };
1165         /** Enable depth write */
1166         bool enableDepthWrite { false };
1167         /** Enable depth bounds test */
1168         bool enableDepthBoundsTest { false };
1169         /** Enable stencil test */
1170         bool enableStencilTest { false };
1171 
1172         /** Min depth bounds */
1173         float minDepthBounds { 0.0f };
1174         /** Max depth bounds */
1175         float maxDepthBounds { 1.0f };
1176 
1177         /** Depth compare operation */
1178         CompareOp depthCompareOp { CompareOp::CORE_COMPARE_OP_NEVER };
1179         /** Front stencil operation state */
1180         StencilOpState frontStencilOpState {};
1181         /** Back stencil operation state */
1182         StencilOpState backStencilOpState {};
1183     };
1184 
1185     /** Color blend state */
1186     struct ColorBlendState {
1187         /** Attachment */
1188         struct Attachment {
1189             /** Enable blend */
1190             bool enableBlend { false };
1191             /** Color write mask */
1192             ColorComponentFlags colorWriteMask { ColorComponentFlagBits::CORE_COLOR_COMPONENT_R_BIT |
1193                                                  ColorComponentFlagBits::CORE_COLOR_COMPONENT_G_BIT |
1194                                                  ColorComponentFlagBits::CORE_COLOR_COMPONENT_B_BIT |
1195                                                  ColorComponentFlagBits::CORE_COLOR_COMPONENT_A_BIT };
1196 
1197             /** Source color blend factor */
1198             BlendFactor srcColorBlendFactor { BlendFactor::CORE_BLEND_FACTOR_ONE };
1199             /** Destination color blend factor */
1200             BlendFactor dstColorBlendFactor { BlendFactor::CORE_BLEND_FACTOR_ONE };
1201             /** Color blend operation */
1202             BlendOp colorBlendOp { BlendOp::CORE_BLEND_OP_ADD };
1203 
1204             /** Source alpha blend factor */
1205             BlendFactor srcAlphaBlendFactor { BlendFactor::CORE_BLEND_FACTOR_ONE };
1206             /** Destination alpha blend factor */
1207             BlendFactor dstAlphaBlendFactor { BlendFactor::CORE_BLEND_FACTOR_ONE };
1208             /** Alpha blend operation */
1209             BlendOp alphaBlendOp { BlendOp::CORE_BLEND_OP_ADD };
1210         };
1211 
1212         /** Enable logic operation */
1213         bool enableLogicOp { false };
1214         /** Logic operation */
1215         LogicOp logicOp { LogicOp::CORE_LOGIC_OP_NO_OP };
1216 
1217         /** Color blend constants (R, G, B, A) */
1218         float colorBlendConstants[4u] { 0.0f, 0.0f, 0.0f, 0.0f };
1219         /** Color attachment count */
1220         uint32_t colorAttachmentCount { 0 };
1221         /** Color attachments */
1222         Attachment colorAttachments[PipelineStateConstants::MAX_COLOR_ATTACHMENT_COUNT];
1223     };
1224 
1225     /** Input assembly */
1226     struct InputAssembly {
1227         /** Enable primitive restart */
1228         bool enablePrimitiveRestart { false };
1229         /** Primitive topology */
1230         PrimitiveTopology primitiveTopology { PrimitiveTopology::CORE_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST };
1231     };
1232 
1233     /** Input assembly */
1234     InputAssembly inputAssembly;
1235     /** Rasterization state */
1236     RasterizationState rasterizationState;
1237     /** Depth stencil state */
1238     DepthStencilState depthStencilState;
1239     /** Color blend state */
1240     ColorBlendState colorBlendState;
1241 };
1242 
1243 /** Vertex input declaration */
1244 struct VertexInputDeclaration {
1245     /** Vertex input binding description */
1246     struct VertexInputBindingDescription {
1247         /** Binding */
1248         uint32_t binding { ~0u };
1249         /** Stride */
1250         uint32_t stride { 0u };
1251         /** Vertex input rate */
1252         VertexInputRate vertexInputRate { VertexInputRate::CORE_VERTEX_INPUT_RATE_VERTEX };
1253     };
1254 
1255     /** Vertex input attribute description */
1256     struct VertexInputAttributeDescription {
1257         /** Location */
1258         uint32_t location { ~0u };
1259         /** Binding */
1260         uint32_t binding { ~0u };
1261         /** Format */
1262         BASE_NS::Format format { BASE_NS::Format::BASE_FORMAT_UNDEFINED };
1263         /** Offset */
1264         uint32_t offset { 0u };
1265     };
1266 };
1267 
1268 /** Vertex input declaration data */
1269 struct VertexInputDeclarationData {
1270     /** Binding description count */
1271     uint32_t bindingDescriptionCount { 0 };
1272     /** Attribute description count */
1273     uint32_t attributeDescriptionCount { 0 };
1274 
1275     /** Array of binding descriptions */
1276     VertexInputDeclaration::VertexInputBindingDescription
1277         bindingDescriptions[PipelineStateConstants::MAX_VERTEX_BUFFER_COUNT];
1278     /** Array of attribute descriptions */
1279     VertexInputDeclaration::VertexInputAttributeDescription
1280         attributeDescriptions[PipelineStateConstants::MAX_VERTEX_BUFFER_COUNT];
1281 };
1282 
1283 /** Vertex input declaration view */
1284 struct VertexInputDeclarationView {
1285     /** Array of binding descriptions */
1286     BASE_NS::array_view<const VertexInputDeclaration::VertexInputBindingDescription> bindingDescriptions;
1287     /** Array of attribute descriptions */
1288     BASE_NS::array_view<const VertexInputDeclaration::VertexInputAttributeDescription> attributeDescriptions;
1289 };
1290 
1291 /** Shader specialization */
1292 struct ShaderSpecialization {
1293     /** Constant */
1294     struct Constant {
1295         enum class Type : uint32_t {
1296             INVALID = 0,
1297             /** 32 bit boolean value */
1298             BOOL = 1,
1299             /** 32 bit unsigned integer value */
1300             UINT32 = 2,
1301             /** 32 bit signed integer value */
1302             INT32 = 3,
1303             /** 32 bit floating-point value */
1304             FLOAT = 4,
1305         };
1306         /** Shader stage */
1307         ShaderStageFlags shaderStage;
1308         /** ID */
1309         uint32_t id;
1310         /** Type */
1311         Type type;
1312         /** Offset */
1313         uint32_t offset;
1314     };
1315 };
1316 
1317 /** Shader specialization constant view */
1318 struct ShaderSpecializationConstantView {
1319     /** Array of shader specialization constants */
1320     BASE_NS::array_view<const ShaderSpecialization::Constant> constants;
1321 };
1322 
1323 /** Shader specialization constant data view */
1324 struct ShaderSpecializationConstantDataView {
1325     /** Array of shader specialization constants */
1326     BASE_NS::array_view<const ShaderSpecialization::Constant> constants;
1327     /** Data */
1328     BASE_NS::array_view<const uint32_t> data;
1329 };
1330 
1331 /** Buffer offset */
1332 struct BufferOffset {
1333     /** Buffer handle */
1334     RenderHandle handle;
1335     /** Buffer offset in bytes */
1336     uint32_t offset { 0 };
1337 };
1338 
1339 /** Accleration structure types */
1340 enum AccelerationStructureType : uint32_t {
1341     /** Acceleration structure type top level */
1342     CORE_ACCELERATION_STRUCTURE_TYPE_TOP_LEVEL = 0,
1343     /** Acceleration structure type bottom level */
1344     CORE_ACCELERATION_STRUCTURE_TYPE_BOTTOM_LEVEL = 1,
1345     /** Acceleration structure type generic */
1346     CORE_ACCELERATION_STRUCTURE_TYPE_GENERIC = 2,
1347 };
1348 
1349 struct AccelerationStructureBuildRangeInfo {
1350     uint32_t primitiveCount { 0u };
1351     uint32_t primitiveOffset { 0u };
1352     uint32_t firstVertex { 0u };
1353     uint32_t transformOffset { 0u };
1354 };
1355 
1356 /** Additional parameters for geometry */
1357 enum GeometryFlagBits : uint32_t {
1358     /** The geometry does not invoke the any-hit shaders even if present in a hit group */
1359     GEOMETRY_OPAQUE_BIT = 0x00000001,
1360     /** Indicates that the implementation must only call the any-hit shader a single time for each primitive
1361      * in this geometry.
1362      */
1363     GEOMETRY_NO_DUPLICATE_ANY_HIT_INVOCATION_BIT = 0x00000002,
1364 };
1365 /** Geometry flags */
1366 using GeometryFlags = uint32_t;
1367 
1368 /** Acceleratoin structure geometry triangles data */
1369 struct AccelerationStructureGeometryTrianglesInfo {
1370     /** Vertex format */
1371     BASE_NS::Format vertexFormat { BASE_NS::Format::BASE_FORMAT_UNDEFINED };
1372     /** Vertex stride, bytes between each vertex */
1373     uint32_t vertexStride { 0u };
1374     /** Highest index of a vertex for building geom */
1375     uint32_t maxVertex { 0u };
1376     /** Index type */
1377     IndexType indexType { IndexType::CORE_INDEX_TYPE_UINT32 };
1378     /** Index count */
1379     uint32_t indexCount { 0u };
1380 
1381     /** Geometry flags */
1382     GeometryFlags geometryFlags { 0u };
1383 };
1384 
1385 /** Acceleratoin structure geometry triangles data */
1386 struct AccelerationStructureGeometryTrianglesData {
1387     /** Triangles info */
1388     AccelerationStructureGeometryTrianglesInfo info;
1389 
1390     /** Vertex buffer with offset */
1391     BufferOffset vertexData;
1392     /** Index buffer with offset */
1393     BufferOffset indexData;
1394     /** Transform buffer (4x3 matrices), additional */
1395     BufferOffset transformData;
1396 };
1397 
1398 /** Acceleration structure geometry AABBs info */
1399 struct AccelerationStructureGeometryAabbsInfo {
1400     /** Stride, bytes between each AABB (must be a multiple of 8) */
1401     uint32_t stride { 0u };
1402 };
1403 
1404 /** Acceleration structure geometry AABBs data */
1405 struct AccelerationStructureGeometryAabbsData {
1406     /** AABBs info */
1407     AccelerationStructureGeometryAabbsInfo info;
1408     /** Buffer resource and offset for AabbPositions */
1409     BufferOffset data;
1410 };
1411 
1412 /** Acceleration structure geometry instances info */
1413 struct AccelerationStructureGeometryInstancesInfo {
1414     /** Specifies whether data is used as an array of addresses or just an array */
1415     bool arrayOfPointers { false };
1416 };
1417 
1418 /** Acceleration structure geometry instances data */
1419 struct AccelerationStructureGeometryInstancesData {
1420     /** Instances info */
1421     AccelerationStructureGeometryInstancesInfo info;
1422     /** Buffer resource and offset for structures */
1423     BufferOffset data;
1424 };
1425 
1426 /** Build acceleration structure flag bits */
1427 enum BuildAccelerationStructureFlagBits : uint32_t {
1428     /** Can be updated */
1429     CORE_BUILD_ACCELERATION_STRUCTURE_ALLOW_UPDATE_BIT = 0x00000001,
1430     /** Alloc compaction bit. Can be used as a source for compaction. */
1431     CORE_BUILD_ACCELERATION_STRUCTURE_ALLOW_COMPACTION_BIT = 0x00000002,
1432     /** Prefer fast trace. Prioritizes trace performance for build time. */
1433     CORE_BUILD_ACCELERATION_STRUCTURE_PREFER_FAST_TRACE_BIT = 0x00000004,
1434     /** Prefer fast build. Prioritizes fast build for trace performance. */
1435     CORE_BUILD_ACCELERATION_STRUCTURE_PREFER_FAST_BUILD_BIT = 0x00000008,
1436     /** Prefer low memory. Prioritizes the size of the scratch memory and the final acceleration structure,
1437      * potentially at the expense of build time or trace performance */
1438     CORE_BUILD_ACCELERATION_STRUCTURE_LOW_MEMORY_BIT = 0x00000010,
1439 };
1440 /** Build acceleration structure flags */
1441 using BuildAccelerationStructureFlags = uint32_t;
1442 
1443 /** Build acceleration structure mode */
1444 enum BuildAccelerationStructureMode : uint32_t {
1445     /** The destination acceleration structure will be built using the specified geometries */
1446     CORE_BUILD_ACCELERATION_STRUCTURE_MODE_BUILD = 0,
1447     /** The destination acceleration structure will be built using data in a source acceleration structure,
1448      * updated by the specified geometries. */
1449     CORE_BUILD_ACCELERATION_STRUCTURE_MODE_UPDATE = 1,
1450 };
1451 
1452 /** Acceleration structure build geometry info */
1453 struct AccelerationStructureBuildGeometryInfo {
1454     /** Acceleration structure type */
1455     AccelerationStructureType type { AccelerationStructureType::CORE_ACCELERATION_STRUCTURE_TYPE_TOP_LEVEL };
1456     /** Additional flags */
1457     BuildAccelerationStructureFlags flags { 0 };
1458     /** Build mode */
1459     BuildAccelerationStructureMode mode {
1460         BuildAccelerationStructureMode::CORE_BUILD_ACCELERATION_STRUCTURE_MODE_BUILD
1461     };
1462 };
1463 
1464 /** Acceleration structure build geometry data */
1465 struct AccelerationStructureBuildGeometryData {
1466     /** Geometry info */
1467     AccelerationStructureBuildGeometryInfo info;
1468 
1469     /** Handle to existing acceleration structure which is used a src for dst update. */
1470     RenderHandle srcAccelerationStructure;
1471     /** Handle to dst acceleration structure which is to be build. */
1472     RenderHandle dstAccelerationStructure;
1473     /** Handle and offset to build scratch data. */
1474     BufferOffset scratchBuffer;
1475 };
1476 
1477 /** Acceleration structure build sizes.
1478  * The build sizes can be queried from device with AccelerationStructureBuildGeometryInfo.
1479  */
1480 struct AccelerationStructureBuildSizes {
1481     /** Acceleration structure size */
1482     uint32_t accelerationStructureSize { 0u };
1483     /** Update scratch size */
1484     uint32_t updateScratchSize { 0u };
1485     /** Build scratch size */
1486     uint32_t buildScratchSize { 0u };
1487 };
1488 
1489 /** Geometry type.
1490  */
1491 enum GeometryType : uint32_t {
1492     /** Triangles */
1493     CORE_GEOMETRY_TYPE_TRIANGLES = 0,
1494     /** AABBs */
1495     CORE_GEOMETRY_TYPE_AABBS = 1,
1496     /** Instances */
1497     CORE_GEOMETRY_TYPE_INSTANCES = 2,
1498 };
1499 
1500 /** Geometry instance flags.
1501  */
1502 enum GeometryInstanceFlagBits : uint32_t {
1503     /** Disable face culling */
1504     CORE_GEOMETRY_INSTANCE_TRIANGLE_FACING_CULL_DISABLE_BIT = 0x00000001,
1505     /** Invert the facing */
1506     CORE_GEOMETRY_INSTANCE_TRIANGLE_FLIP_FACING_BIT = 0x00000002,
1507     /** Force geometry to be treated as opaque */
1508     CORE_GEOMETRY_INSTANCE_FORCE_OPAQUE_BIT = 0x00000004,
1509     /** Removes opaque bit from geometry. Can be overriden with SPIR-v OpaqueKHR flag */
1510     CORE_GEOMETRY_INSTANCE_FORCE_NO_OPAQUE_BIT = 0x00000008,
1511 };
1512 using GeometryInstanceFlags = uint32_t;
1513 
1514 /** Acceleration structure instance info.
1515  */
1516 struct AccelerationStructureInstanceInfo {
1517     /** Affine transform matrix (4x3 used) */
1518     // BASE_NS::Math::Mat4X4 transform{};
1519     float transform[4][4];
1520     /** User specified index accessable in ray shaders with InstanceCustomIndexKHR (24 bits) */
1521     uint32_t instanceCustomIndex { 0u };
1522     /** Mask, a visibility mask for geometry (8 bits). Instance may only be hit if cull mask & instance.mask != 0. */
1523     uint8_t mask { 0u };
1524     /** GeometryInstanceFlags for this instance */
1525     GeometryInstanceFlags flags { 0u };
1526 };
1527 
1528 /** Acceleration structure instance data.
1529  */
1530 struct AccelerationStructureInstanceData {
1531     /** Instance info */
1532     AccelerationStructureInstanceInfo info;
1533 
1534     /** Acceleration structure handle */
1535     RenderHandle accelerationStructureReference;
1536 };
1537 /** @} */
1538 RENDER_END_NAMESPACE()
1539 
1540 #endif // API_RENDER_DEVICE_PIPELINE_STATE_DESC_H
1541