1 /*
2  * Copyright 2024 Institute of Software, Chinese Academy of Sciences.
3  * Licensed under the Apache License, Version 2.0 (the "License");
4  * you may not use this file except in compliance with the License.
5  * You may obtain a copy of the License at
6  *
7  * http://www.apache.org/licenses/LICENSE-2.0
8  *
9  * Unless required by applicable law or agreed to in writing, software
10  * distributed under the License is distributed on an "AS IS" BASIS,
11  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12  * See the License for the specific language governing permissions and
13  * limitations under the License.
14  */
15 
16 #ifndef UNWIND_RISCV64_DEFINE_H
17 #define UNWIND_RISCV64_DEFINE_H
18 
19 #include <cinttypes>
20 #include <string>
21 #include <vector>
22 
23 namespace OHOS {
24 namespace HiviewDFX {
25 #define REGS_PRINT_LEN 1024
26 #define DWARF_PRESERVED_REGS_NUM 97
27 
28 #ifdef REG_SP
29 #undef REG_SP
30 #endif
31 #ifdef REG_PC
32 #undef REG_PC
33 #endif
34 
35 enum RegsEnumRiscv64 : uint16_t {
36     REG_RISCV64_X0 = 0,
37     REG_RISCV64_X1,
38     REG_RISCV64_X2,
39     REG_RISCV64_X3,
40     REG_RISCV64_X4,
41     REG_RISCV64_X5,
42     REG_RISCV64_X6,
43     REG_RISCV64_X7,
44     REG_RISCV64_X8,
45     REG_RISCV64_X9,
46     REG_RISCV64_X10,
47     REG_RISCV64_X11,
48     REG_RISCV64_X12,
49     REG_RISCV64_X13,
50     REG_RISCV64_X14,
51     REG_RISCV64_X15,
52     REG_RISCV64_X16,
53     REG_RISCV64_X17,
54     REG_RISCV64_X18,
55     REG_RISCV64_X19,
56     REG_RISCV64_X20,
57     REG_RISCV64_X21,
58     REG_RISCV64_X22,
59     REG_RISCV64_X23,
60     REG_RISCV64_X24,
61     REG_RISCV64_X25,
62     REG_RISCV64_X26,
63     REG_RISCV64_X27,
64     REG_RISCV64_X28,
65     REG_RISCV64_X29,
66     REG_RISCV64_X30,
67     REG_RISCV64_X31,
68     REG_RISCV64_PC,
69     REG_RISCV64_LAST,
70 
71     REG_SP = REG_RISCV64_X2,
72     REG_LR = REG_RISCV64_X0,
73     REG_FP = REG_RISCV64_X8,
74     REG_PC = REG_RISCV64_PC,
75     REG_EH = REG_RISCV64_X0,
76     REG_LAST = REG_RISCV64_LAST,
77 };
78 
79 static const std::vector<uint16_t> QUT_REGS {
80     REG_RISCV64_X0,
81     REG_RISCV64_X31,
82     REG_SP,
83     REG_PC,
84     REG_LR,
85 };
86 
87 struct RegsUserRiscv64 {
88     uint64_t regs[31];
89     uint64_t sp;
90     uint64_t pc;
91     uint64_t pstate;
92 };
93 
94 typedef struct UnwindUContext {
95     RegsUserRiscv64 userRegs;
96 } UnwindUContext_t;
97 } // namespace HiviewDFX
98 } // namespace OHOS
99 #endif
100