1 /* 2 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. 3 * 4 * HDF is dual licensed: you can use it either under the terms of 5 * the GPL, or the BSD license, at your option. 6 * See the LICENSE file in the root of this repository for complete details. 7 */ 8 9 #ifndef MMC_PROTOCOL_H 10 #define MMC_PROTOCOL_H 11 12 #include "hdf_base.h" 13 14 #ifdef __cplusplus 15 #if __cplusplus 16 extern "C" { 17 #endif 18 #endif /* __cplusplus */ 19 20 #define CID_LEN 4 21 #define CID_BITS 128 22 #define CID_BYTES_LEN 16 23 #define CID_PNM_LEN 8 24 #define CID_PNM_START_BIT 96 25 #define CSD_LEN 4 26 #define CSD_BITS 128 27 #define EXT_CSD_BYTES_LEN 512 28 #define BITS_PER_BYTE 8 29 #define SCR_LEN 2 30 #define SCR_BYTES_LEN 8 31 #define SCR_BITS 64 32 #define DSR_BITS 16 33 #define SSR_LEN 16 34 #define SSR_BYTES_LEN 64 35 #define SSR_BITS 512 36 37 /* The basic unit data transfer is a block whose maximum size is always 512 bytes. */ 38 #define BYTES_PER_BLOCK 512 39 #define MMC_MAX_BLOCKSIZE_SHIFT 9 40 41 #define SDIO_BLOCK_TRANSFER_MAX_BLKNUM 511 42 43 /* mmc commands */ 44 enum MmcCmdCode { 45 GO_IDLE_STATE = 0, /* resets all cards to idle state */ 46 SEND_OP_COND = 1, /* 47 * asks all cards in idle state to send their operation conditions register contents 48 * in the response on the CMD line. 49 */ 50 ALL_SEND_CID = 2, /* asks all cards to send their CID numbers on the CMD line. */ 51 SET_RELATIVE_ADDR = 3, /* assigns relative address to the card. */ 52 SET_DSR = 4, /* programs the DSR of all cards. */ 53 SWITCH = 6, /* Switches the mode of operation of the selected card or modifies the EXT_CSD registers. */ 54 SELECT_CARD = 7, /* 55 * command toggles a card between the stand-by and transfer states or between the programming and 56 * disconnect states. In both cases the card is selected by its own relative address and gets 57 * deselected by any other address; address 0 deselects all. 58 */ 59 SEND_EXT_CSD = 8, /* The card sends its EXT_CSD register as a block of data. */ 60 SEND_CSD = 9, /* addressed card sends its card-specific data (CSD) on the CMD line. */ 61 SEND_CID = 10, /* addressed card sends its card identification (CID) on CMD the line. */ 62 READ_DAT_UNTIL_STOP = 11, /* 63 * reads data stream from the card, starting at the given address, 64 * until a STOP_TRANSMISSION follows. 65 */ 66 STOP_TRANSMISSION = 12, /* 67 * Terminates a read/write stream/multiple block operation. 68 * When CMD12 is used to terminate a read transaction the card will respond with R1. 69 * When it is used to stop a write transaction the card will respondwith R1b. 70 */ 71 SEND_STATUS = 13, /* addressed card sends its status register. */ 72 GO_INACTIVE_STATE = 15, /* 73 * sets the card to inactive state in order to protect the card stack against 74 * communication breakdowns. 75 */ 76 SET_BLOCKLEN = 16, /* 77 * sets the block length (in bytes) for all following block commands (read and write). 78 * Default block length is specified in the CSD. 79 */ 80 READ_SINGLE_BLOCK = 17, /* reads a block of the size selected by the SET_BLOCKLEN command. */ 81 READ_MULTIPLE_BLOCK = 18, /* 82 * continuously transfers data blocks from card to host until interrupted 83 * by a stop command or the requested number of data block transmitted. 84 */ 85 WRITE_DAT_UNTIL_STOP = 20, /* 86 * writes data stream from the host, starting at the given address, 87 * until a STOP_TRANSMISSION follows. 88 */ 89 SEND_TUNING_BLOCK_HS200 = 21, /* 90 * Dedicated for HS200 mode, used to optimize host sampling points. 91 * The host sends the CMD21 command, and the device sends the data block in tuning 92 * mode. The host collects data at different sampling points to find the best 93 * sampling point. 94 */ 95 SET_BLOCK_COUNT = 23, /* 96 * Defines the number of blocks which are going to be transferred in the immediately 97 * succeeding multiple block read or write command. 98 */ 99 WRITE_BLOCK = 24, /* writes a block of the size selected by the SET_BLOCKLEN command. */ 100 WRITE_MULTIPLE_BLOCK = 25, /* 101 * continuously writes blocks of data until a STOP_TRANSMISSION follows 102 * or the requested number of block received. 103 */ 104 PROGRAM_CID = 26, /* 105 * programming of the card identification register. This command shall be issued only once 106 * per card. The card contains hardware to prevent this operation after the first programming. 107 * Normally this command is reserved for the manufacturer. 108 */ 109 PROGRAM_CSD = 27, /* programming of the programmable bits of the CSD. */ 110 SET_WRITE_PROT = 28, /* 111 * if the card has write protection features, 112 * this command sets the write protection bit of the addressed group. 113 * The properties of write protection are coded in the card specific data (WP_GRP_SIZE). 114 */ 115 CLR_WRITE_PROT = 29, /* 116 * if the card provides write protection features, 117 * this command clears the write protection bit of the addressed group. 118 */ 119 SEND_WRITE_PROT = 30, /* 120 * if the card provides write protection features, 121 * this command asks the card to send the status of the write protection bits. 122 */ 123 ERASE_GROUP_START = 35, /* sets the address of the first erase group within a range to be selected for erase. */ 124 ERASE_GROUP_END = 36, /* 125 * sets the address of the last erase group within a continuous 126 * range to be selected for erase. 127 */ 128 MMC_ERASE = 38, /* erases all previously selected write blocks. */ 129 MMC_FAST_IO = 39, /* 130 * used to write and read 8 bit (register) data fields. The command addresses a card and 131 * a register and provides the data for writing if the write flag is set. The R4 response 132 * contains data read from the addressed register. This command accesses application 133 * dependent registers which are not defined in the MultiMediaCard standard. 134 */ 135 GO_IRQ_STATE = 40, /* Sets the system into interrupt mode. */ 136 LOCK_UNLOCK = 42, /* 137 * Used to set/reset the password or lock/ unlock the card. 138 * The size of the data block is set by the SET_BLOCK_LEN command. 139 */ 140 APP_CMD = 55, /* 141 * Indicates to the card that the next command is an application specific command 142 * rather than a standard command. 143 */ 144 GEN_CMD = 56, /* 145 * Used either to transfer a data block to the card or to get a data block from the card 146 * for general purpose / application specific commands. 147 * The size of the data block shall be set by the SET_BLOCK_LEN command. 148 */ 149 }; 150 151 #define MMC_CARD_BUSY_STATUS 0x80000000 /* Card Power up status bit */ 152 153 /* OCR bit definitions */ 154 enum MmcOcrBitsMark { 155 MMC_OCR_1V65_1V95 = 0x00000080, /* VDD 1.65V ~ 1.95V */ 156 MMC_OCR_2V0_2V1 = 0x00000100, /* VDD 2.0V ~ 2.1V */ 157 MMC_OCR_2V1_2V2 = 0x00000200, /* VDD 2.1V ~ 2.2V */ 158 MMC_OCR_2V2_2V3 = 0x00000400, /* VDD 2.2V ~ 2.3V */ 159 MMC_OCR_2V3_2V4 = 0x00000800, /* VDD 2.3V ~ 2.4V */ 160 MMC_OCR_2V4_2V5 = 0x00001000, /* VDD 2.4V ~ 2.5V */ 161 MMC_OCR_2V5_2V6 = 0x00002000, /* VDD 2.5V ~ 2.6V */ 162 MMC_OCR_2V6_2V7 = 0x00004000, /* VDD 2.6V ~ 2.7V */ 163 MMC_OCR_2V7_2V8 = 0x00008000, /* VDD 2.7V ~ 2.8V */ 164 MMC_OCR_2V8_2V9 = 0x00010000, /* VDD 2.8V ~ 2.9V */ 165 MMC_OCR_2V9_3V0 = 0x00020000, /* VDD 2.9V ~ 3.0V */ 166 MMC_OCR_3V0_3V1 = 0x00040000, /* VDD 3.0V ~ 3.1V */ 167 MMC_OCR_3V1_3V2 = 0x00080000, /* VDD 3.1V ~ 3.2V */ 168 MMC_OCR_3V2_3V3 = 0x00100000, /* VDD 3.2V ~ 3.3V */ 169 MMC_OCR_3V3_3V4 = 0x00200000, /* VDD 3.3V ~ 3.4V */ 170 MMC_OCR_3V4_3V5 = 0x00400000, /* VDD 3.4V ~ 3.5V */ 171 MMC_OCR_3V5_3V6 = 0x00800000, /* VDD 3.5V ~ 3.6V */ 172 }; 173 174 /* ocr register describe */ 175 union MmcOcr { 176 uint32_t ocrData; 177 struct OcrBits { 178 uint32_t reserved : 7; 179 uint32_t vdd1v65To1v95 : 1; /* bit:7 voltage 1.65 ~ 1.95 */ 180 uint32_t vdd2v0To2v1 : 1; /* bit:8 voltage 2.0 ~ 2.1 */ 181 uint32_t vdd2v1To2v2 : 1; /* bit:9 voltage 2.1 ~ 2.2 */ 182 uint32_t vdd2v2To2v3 : 1; /* bit:10 voltage 2.2 ~ 2.3 */ 183 uint32_t vdd2v3To2v4 : 1; /* bit:11 voltage 2.3 ~ 2.4 */ 184 uint32_t vdd2v4To2v5 : 1; /* bit:12 voltage 2.4 ~ 2.5 */ 185 uint32_t vdd2v5To2v6 : 1; /* bit:13 voltage 2.5 ~ 2.6 */ 186 uint32_t vdd2v6To2v7 : 1; /* bit:14 voltage 2.6 ~ 2.7 */ 187 uint32_t vdd2v7To2v8 : 1; /* bit:15 voltage 2.7 ~ 2.8 */ 188 uint32_t vdd2v8To2v9 : 1; /* bit:16 voltage 2.8 ~ 2.9 */ 189 uint32_t vdd2v9To3v0 : 1; /* bit:17 voltage 2.9 ~ 3.0 */ 190 uint32_t vdd3v0To3v1 : 1; /* bit:18 voltage 3.0 ~ 3.1 */ 191 uint32_t vdd3v1To3v2 : 1; /* bit:19 voltage 3.1 ~ 3.2 */ 192 uint32_t vdd3v2To3v3 : 1; /* bit:20 voltage 3.2 ~ 3.3 */ 193 uint32_t vdd3v3To3v4 : 1; /* bit:21 voltage 3.3 ~ 3.4 */ 194 uint32_t vdd3v4To3v5 : 1; /* bit:22 voltage 3.4 ~ 3.5 */ 195 uint32_t vdd3v5To3v6 : 1; /* bit:23 voltage 3.5 ~ 3.6 */ 196 uint32_t s18r : 1; /* bit:24 switch to 1.8v accepted */ 197 uint32_t reserved2 : 2; 198 uint32_t sdioMemoryPreset : 1; /* bit:27 sdio memory present */ 199 uint32_t sdXpc : 1; /* bit:28 XPC for ACMD41 */ 200 uint32_t sdUhsII : 1; /* bit:29 UHSII for resp of ACMD41 */ 201 uint32_t hcs : 1; /* bit:30 support high capacity */ 202 uint32_t busy : 1; /* bit:31 This bit is set to LOW if the card has not finished the power up routine */ 203 } bits; 204 }; 205 206 /* SEND_STATUS rsp, card status bits */ 207 enum MmcRspCardStatus { 208 OUT_OF_RANGE = (1 << 31), /* The command's argument was out of the allowed range for this card. */ 209 ADDRESS_ERROR = (1 << 30), /* A misaligned address which did not match the block length was used in the command. */ 210 BLOCK_LEN_ERROR = (1 << 29), /* The transferred block length is not allowed for this card, 211 * or the number of transferred bytes does not match the block length. 212 */ 213 ERASE_SEQ_ERROR = (1 << 28), /* An error in the sequence of erase commands occurred. */ 214 ERASE_PARAM = (1 << 27), /* An invalid selection of erase groups for erase occurred. */ 215 WP_VIOLATION = (1 << 26), /* Attempt to program a write protected block. */ 216 CARD_IS_LOCKED = (1 << 25), /* When set, signals that the card is locked by the host. */ 217 LOCK_UNLOCK_FAILED = (1 << 24), /* Set when a sequence or password error has been detected in lock/unlock card 218 * command or if there was an attempt to access a locked card. 219 */ 220 COM_CRC_ERROR = (1 << 23), /* The CRC check of the previous command failed. */ 221 ILLEGAL_COMMAND = (1 << 22), /* Command not legal for the card state. */ 222 CARD_ECC_FAILED = (1 << 21), /* Card internal ECC was applied but failed to correct the data. */ 223 CC_ERROR = (1 << 20), /* Internal card controller error. */ 224 GENERAL_ERROR = (1 << 19), /* A general or an unknown error occurred during the operation. */ 225 UNDERRUN = (1 << 18), /* The card could not sustain data transfer in stream read mode. */ 226 OVERRUN = (1 << 17), /* The card could not sustain data programming in stream write mode. */ 227 CID_CSD_OVERWRITE = (1 << 16), /* can be either one of the following errors: 228 * - The CID register has been already written and can not be overwritten 229 * - The read only section of the CSD does not match the card content. 230 * - An attempt to reverse the copy (set as original) or permanent WP (unprotected) 231 * bits was made. 232 */ 233 WP_ERASE_SKIP = (1 << 15), /* Only partial address space was erased due to existing write protected blocks. */ 234 CARD_ECC_DISABLED = (1 << 14), /* The command has been executed without using the internal ECC. */ 235 ERASE_RESET = (1 << 13), /* An erase sequence was cleared before executing because an out of erase sequence 236 * command was received. 237 */ 238 READY_FOR_DATA = (1 << 8), /* corresponds to buffer empty signalling on the bus. */ 239 SWITCH_ERROR = (1 << 7), /* If set, the card did not switch to the expected mode as requested by 240 * the SWITCH command. 241 */ 242 URGENT_BKOPS = (1 << 6), /* If set, device needs to perform background operations urgently. 243 * Host can check EXT_CSD field BKOPS_STATUS for the detailed level. 244 */ 245 IS_APP_CMD = (1 << 5), /* The card will expect ACMD, or indication that the command has been 246 * interpreted as ACMD. 247 */ 248 }; 249 250 /* 251 * The state of the card when receiving the command. If the command execution causes a 252 * state change, it will be visible to the host in the response to the next command. 253 * The four bits([12:9]) are interpreted as a binary coded number between 0 and 15. 254 */ 255 #define MMC_CARD_CURRENT_STATE(x) (((x) & 0x00001E00) >> 9) /* sx, b (4 bits) */ 256 enum MmcCardCurrentState { 257 STATE_IDLE = 0, 258 STATE_READY = 1, 259 STATE_IDENT = 2, 260 STATE_STBY = 3, 261 STATE_TRAN = 4, 262 STATE_DATA = 5, 263 STATE_RCV = 6, 264 STATE_PRG = 7, 265 STATE_DIS = 8, 266 }; 267 268 /* addressed (point-to-point) commands (ac) sent on CMD line, response on CMD line. */ 269 #define MMC_CMD_TYPE_AC (0x0 << 5) 270 271 /* 272 * addressed (point-to-point) data transfer commands (adtc) sent on CMD line, response on CMD line, 273 * data transfer on DAT line. 274 */ 275 #define MMC_CMD_TYPE_ADTC (0x1 << 5) 276 277 /* broadcast commands (bc) sent on CMD line, no response. */ 278 #define MMC_CMD_TYPE_BC (0x2 << 5) 279 280 /* broadcast commands with response (bcr) sent on CMD line, response (all cards simultaneously) on CMD line. */ 281 #define MMC_CMD_TYPE_BCR (0x3 << 5) 282 283 #define MMC_CMD_RESP_SIZE 4 284 /* cmd resp type */ 285 #define RESP_PRESENT (1 << 0) 286 #define RESP_136 (1 << 1) /* 136 bit response */ 287 #define RESP_CRC (1 << 2) /* expect valid crc */ 288 #define RESP_BUSY (1 << 3) /* card may send busy */ 289 #define RESP_CMDCODE (1 << 4) /* response contains opcode */ 290 291 #define MMC_RESP_NONE 0 292 #define MMC_RESP_R1 (RESP_PRESENT | RESP_CMDCODE | RESP_CRC) 293 #define MMC_RESP_R1B (RESP_PRESENT | RESP_CMDCODE | RESP_BUSY | RESP_CRC) 294 #define MMC_RESP_R2 (RESP_PRESENT | RESP_136 | RESP_CRC) 295 #define MMC_RESP_R3 (RESP_PRESENT) 296 #define MMC_RESP_R4 (RESP_PRESENT) 297 #define MMC_RESP_R5 (RESP_PRESENT | RESP_CMDCODE | RESP_CRC) 298 #define MMC_RESP_R6 (RESP_PRESENT | RESP_CMDCODE | RESP_CRC) 299 #define MMC_RESP_R7 (RESP_PRESENT | RESP_CMDCODE | RESP_CRC) 300 301 #define MMC_RESP_TYPE(cmd) ((cmd)->respType & (RESP_PRESENT | RESP_136 | RESP_CRC | RESP_BUSY | RESP_CMDCODE)) 302 303 #define MMC_RESP_SPI_S1 (1 << 7) 304 #define MMC_RESP_SPI_S2 (1 << 8) 305 #define MMC_RESP_SPI_B4 (1 << 9) 306 #define MMC_RESP_SPI_BUSY (1 << 10) 307 308 #define MMC_RESP_SPI_R1 (MMC_RESP_SPI_S1) 309 #define MMC_RESP_SPI_R1B (MMC_RESP_SPI_S1 | MMC_RESP_SPI_BUSY) 310 #define MMC_RESP_SPI_R2 (MMC_RESP_SPI_S1 | MMC_RESP_SPI_S2) 311 #define MMC_RESP_SPI_R3 (MMC_RESP_SPI_S1 | MMC_RESP_SPI_B4) 312 #define MMC_RESP_SPI_R4 (MMC_RESP_SPI_S1 | MMC_RESP_SPI_B4) 313 #define MMC_RESP_SPI_R5 (MMC_RESP_SPI_S1 | MMC_RESP_SPI_S2) 314 #define MMC_RESP_SPI_R7 (MMC_RESP_SPI_S1 | MMC_RESP_SPI_B4) 315 316 enum MmcCsdStructure { 317 MMC_CSD_STRUCTURE_VER_1_0 = 0, 318 MMC_CSD_STRUCTURE_VER_1_1 = 1, 319 MMC_CSD_STRUCTURE_VER_1_2 = 2, /* Specification Version 4.1-4.2-4.3 */ 320 MMC_CSD_STRUCTURE_VER_OTHER = 3, /* Version is coded int the CSD_STRUCTURE byte in the EXT_CSD register. */ 321 }; 322 323 enum MmcCsdSpecVersion { 324 MMC_CSD_SPEC_VER_0 = 0, 325 MMC_CSD_SPEC_VER_1 = 1, 326 MMC_CSD_SPEC_VER_2 = 2, 327 MMC_CSD_SPEC_VER_3 = 3, 328 MMC_CSD_SPEC_VER_4 = 4, 329 }; 330 331 enum MmcCsdCardCmdClass { 332 MMC_CSD_CCC_BASIC = (1 << 0), 333 MMC_CSD_CCC_BLOCK_READ = (1 << 2), 334 MMC_CSD_CCC_BLOCK_WRITE = (1 << 4), 335 MMC_CSD_CCC_ERASE = (1 << 5), 336 MMC_CSD_CCC_WRITE_PROT = (1 << 6), 337 MMC_CSD_CCC_LOCK_CARD = (1 << 7), 338 MMC_CSD_CCC_APP_SPEC = (1 << 8), 339 MMC_CSD_CCC_IO_MODE = (1 << 9), 340 MMC_CSD_CCC_SWITCH = (1 << 10), 341 }; 342 343 enum MmcBusMode { 344 MMC_BUS_MODE_NULL = 0, 345 MMC_1_2V_DDR_MODE = 1, 346 MMC_1_8V_DDR_MODE = 2, 347 MMC_1_2V_SDR_MODE = 3, 348 MMC_1_8V_SDR_MODE = 4, 349 }; 350 351 /* CID register define */ 352 struct MmcCid { 353 uint32_t mid; /* Manufacturer ID */ 354 char pnm[CID_PNM_LEN]; /* Product name */ 355 uint32_t psn; /* Product serial number */ 356 uint16_t oid; /* OEM/Application ID */ 357 uint16_t year; /* Manufacturing date: The y field */ 358 uint8_t month; /* Manufacturing date: The m field */ 359 /* 360 * The product revision is composed of two Binary Coded Decimal (BCD) digits, four bits each, 361 * representing an "n.m" revision number. 362 */ 363 uint8_t hwPrv; /* Product revision: n */ 364 uint8_t fwPrv; /* Product revision: m */ 365 }; 366 367 /* CSD register define */ 368 struct MmcCsd { 369 uint8_t structure; /* CSD_STRUCTURE: [127:126] */ 370 uint8_t specVers; /* emmc-->SPEC_VERS: [125:122] */ 371 uint16_t ccc; /* card command classes: [95:84] */ 372 uint16_t taccClks; /* data read access-time-2 in CLK(NSAC)[111:104]: The unit for NSAC is 100 clock cycles. */ 373 uint32_t taccNs; /* data read access-time-1(TAAC)[119:112]: time unit[2:0] * time value[6:3] */ 374 uint32_t cSize; /* device size(C_SIZE): [73:62] */ 375 uint32_t r2wFactor; /* write speed factor(R2W_FACTOR): [28:26] */ 376 uint32_t maxDtr; /* max data transfer rate[103:96]: transfer rate unit[2:0] * time value[6:3] */ 377 uint32_t eraseSize; /* erase sector size: [45:39], emmc and sd are different. */ 378 uint32_t readBlkLen; /* max read data block length(READ_BL_LEN): [83:80] */ 379 uint32_t writeBlkLen; /* max write data block length(WRITE_BL_LEN): [25:22] */ 380 uint32_t capacity; /* see CSD Field C_SIZE. */ 381 uint32_t rdPartial : 1, /* partial blocks for read allowed: [79] */ 382 rdMisalign : 1, /* read block misalignment: [77] */ 383 wrPartial : 1, /* partial blocks for write allowed: [21] */ 384 wrMisalign : 1; /* write block misalignment: [78] */ 385 }; 386 387 /* Emmc Extended CSD fields */ 388 enum EmmcExtendedCsdField { 389 EMMC_EXT_CSD_ENH_START_ADDR = 136, /* R/W, 4 bytes */ 390 EMMC_EXT_CSD_ENH_SIZE_MULT = 140, /* R/W, 3 bytes */ 391 EMMC_EXT_CSD_GP_SIZE_MULT = 143, /* R/W, 12 bytes */ 392 EMMC_EXT_CSD_PARTITIONS_ATTRIBUTE = 156, /* R/W */ 393 EMMC_EXT_CSD_PARTITIONING_SUPPORT = 160, /* RO */ 394 EMMC_EXT_CSD_HPI_MGMT = 161, /* R/W */ 395 EMMC_EXT_CSD_RST_N_FUNCTION = 162, /* R/W */ 396 EMMC_EXT_CSD_WR_REL_PARAM = 166, /* RO */ 397 EMMC_EXT_CSD_BOOT_WP = 173, /* R/W */ 398 EMMC_EXT_CSD_ERASE_GROUP_DEF = 175, /* R/W */ 399 EMMC_EXT_CSD_PARTITION_CONFIG = 179, /* R/W */ 400 EMMC_EXT_CSD_ERASED_MEM_CONT = 181, /* RO */ 401 EMMC_EXT_CSD_BUS_WIDTH = 183, /* R/W */ 402 EMMC_EXT_CSD_STROBE_SUPPORT = 184, /* RO */ 403 EMMC_EXT_CSD_HS_TIMING = 185, /* R/W */ 404 EMMC_EXT_CSD_POWER_CLASS = 187, /* R/W */ 405 EMMC_EXT_CSD_REV = 192, /* RO */ 406 EMMC_EXT_CSD_STRUCTURE = 194, /* RO */ 407 EMMC_EXT_CSD_CARD_TYPE = 196, /* RO */ 408 EMMC_EXT_CSD_OUT_OF_INTERRUPT_TIME = 198, /* RO */ 409 EMMC_EXT_CSD_PARTITION_SWITCH_TIME = 199, /* RO */ 410 EMMC_EXT_CSD_PWR_CL_52_195 = 200, /* RO */ 411 EMMC_EXT_CSD_PWR_CL_26_195 = 201, /* RO */ 412 EMMC_EXT_CSD_PWR_CL_52_360 = 202, /* RO */ 413 EMMC_EXT_CSD_PWR_CL_26_360 = 203, /* RO */ 414 EMMC_EXT_CSD_SEC_CNT = 212, /* RO, 4 bytes */ 415 EMMC_EXT_CSD_S_A_TIMEOUT = 217, /* RO */ 416 EMMC_EXT_CSD_HC_WP_GRP_SIZE = 221, /* RO */ 417 EMMC_EXT_CSD_REL_WR_SEC_C = 222, /* RO */ 418 EMMC_EXT_CSD_ERASE_TIMEOUT_MULT = 223, /* RO */ 419 EMMC_EXT_CSD_HC_ERASE_GRP_SIZE = 224, /* RO */ 420 EMMC_EXT_CSD_BOOT_MULTI = 226, /* RO */ 421 EMMC_EXT_CSD_SEC_TRIM_MULT = 229, /* RO */ 422 EMMC_EXT_CSD_SEC_ERASE_MULT = 230, /* RO */ 423 EMMC_EXT_CSD_SEC_FEATURE_SUPPORT = 231, /* RO */ 424 EMMC_EXT_CSD_TRIM_MULT = 232, /* RO */ 425 EMMC_EXT_CSD_PWR_CL_200_195 = 236, /* RO */ 426 EMMC_EXT_CSD_PWR_CL_200_360 = 237, /* RO */ 427 EMMC_EXT_CSD_PWR_CL_DDR_52_195 = 238, /* RO */ 428 EMMC_EXT_CSD_PWR_CL_DDR_52_360 = 239, /* RO */ 429 EMMC_EXT_CSD_HPI_FEATURES = 503, /* RO */ 430 }; 431 432 #define EMMC_EXT_CSD_SEC_CNT_BYTES 4 433 #define EMMC_EXT_CSD_ENH_START_ADDR_BYTES 4 434 #define EMMC_EXT_CSD_GP_SIZE_MULT_BYTES 12 435 #define EMMC_EXT_CSD_ENH_SIZE_MULT_BYTES 3 436 437 /* PARTITION_CONFIG[179], bit2-bit0: PARTITION_ACCESS. */ 438 #define EMMC_EXT_CSD_PART_CONFIG_ACCESS_MASK (0x7) 439 440 enum EmmcExtCsdStructure { 441 EMMC_EXT_CSD_STRUCTURE_VER_1_0 = 0, 442 EMMC_EXT_CSD_STRUCTURE_VER_1_1 = 1, 443 EMMC_EXT_CSD_STRUCTURE_VER_1_2 = 2, /* Specification Version 4.1-4.2-4.3-4.4 */ 444 EMMC_EXT_CSD_STRUCTURE_VER_OTHER = 3, /* Reserved for future use. */ 445 }; 446 447 enum EmmcExtCsdRev { 448 EMMC_EXT_CSD_REV_1_0 = 0, /* Revision 1.0(for MMC v4.0) */ 449 EMMC_EXT_CSD_REV_1_1 = 1, /* Revision 1.1(for MMC v4.1) */ 450 EMMC_EXT_CSD_REV_1_2 = 2, /* Revision 1.2(for MMC v4.2) */ 451 EMMC_EXT_CSD_REV_1_3 = 3, /* Revision 1.3(for MMC v4.3) */ 452 EMMC_EXT_CSD_REV_1_4 = 4, /* Revision 1.4(Obsolete) */ 453 EMMC_EXT_CSD_REV_1_5 = 5, /* Revision 1.5(for MMC v4.4.1) */ 454 EMMC_EXT_CSD_REV_OTHER = 6, /* Reserved */ 455 }; 456 457 #define EMMC_EXT_CSD_CARD_TYPE_MASK 0x3F /* Mask out reserved bits */ 458 459 enum EmmcExtCsdCardType { 460 EMMC_EXT_CSD_CARD_TYPE_26 = 0x01, /* Card can run at 26MHz */ 461 EMMC_EXT_CSD_CARD_TYPE_52 = 0x02, /* Card can run at 52MHz */ 462 EMMC_EXT_CSD_CARD_TYPE_DDR_1_8V = 0x04, /* DDR mode @1.8V or 3V I/O, Card can run at 52MHz */ 463 EMMC_EXT_CSD_CARD_TYPE_DDR_1_2V = 0x08, /* DDR mode @1.2V I/O, Card can run at 52MHz */ 464 EMMC_EXT_CSD_CARD_TYPE_DDR_52 = 0x0C, /* EMMC_EXT_CSD_CARD_TYPE_DDR_1_8V | EMMC_EXT_CSD_CARD_TYPE_DDR_1_2V */ 465 EMMC_EXT_CSD_CARD_TYPE_SDR_1_8V = 0x10, /* Card can run at 200MHz */ 466 EMMC_EXT_CSD_CARD_TYPE_SDR_1_8V_ALL = 0x13, 467 EMMC_EXT_CSD_CARD_TYPE_SDR_1_8V_ALL_DDR_1_8V = 0x17, 468 EMMC_EXT_CSD_CARD_TYPE_SDR_1_8V_ALL_DDR_1_2V = 0x1B, 469 EMMC_EXT_CSD_CARD_TYPE_SDR_1_8V_ALL_DDR_52 = 0x1F, 470 EMMC_EXT_CSD_CARD_TYPE_SDR_1_2V = 0x20, /* SDR mode @1.2V I/O, Card can run at 200MHz */ 471 EMMC_EXT_CSD_CARD_TYPE_SDR_1_2V_ALL = 0x23, 472 EMMC_EXT_CSD_CARD_TYPE_SDR_1_2V_ALL_DDR_1_8V = 0x27, 473 EMMC_EXT_CSD_CARD_TYPE_SDR_1_2V_ALL_DDR_1_2V = 0x2B, 474 EMMC_EXT_CSD_CARD_TYPE_SDR_1_2V_ALL_DDR_52 = 0x2F, 475 EMMC_EXT_CSD_CARD_TYPE_SDR_200 = 0x30, 476 EMMC_EXT_CSD_CARD_TYPE_SDR_ALL = 0x33, 477 EMMC_EXT_CSD_CARD_TYPE_SDR_ALL_DDR_1_8V = 0x37, 478 EMMC_EXT_CSD_CARD_TYPE_SDR_ALL_DDR_1_2V = 0x3B, 479 EMMC_EXT_CSD_CARD_TYPE_SDR_ALL_DDR_52 = 0x3F, 480 EMMC_EXT_CSD_CARD_TYPE_HS400_1_8V = 0x40, /* Card can run at 200MHz DDR, 1.8V */ 481 EMMC_EXT_CSD_CARD_TYPE_HS400_1_2V = 0x80, /* Card can run at 200MHz DDR, 1.2V */ 482 EMMC_EXT_CSD_CARD_TYPE_HS400 = 0xC0, 483 EMMC_EXT_CSD_CARD_TYPE_HS400ES = 0x100, /* Card can run at HS400ES */ 484 }; 485 486 enum EmmcExtCsdHighSpeedMaxDtr { 487 EMMC_EXT_CSD_HIGH_SPEED_26 = 26000000, /* 26M */ 488 EMMC_EXT_CSD_HIGH_SPEED_52 = 52000000, /* 52M */ 489 EMMC_EXT_CSD_HIGH_SPEED_200 = 200000000, /* 200M */ 490 }; 491 492 /* High Priority Interrupt */ 493 enum EmmcExtCsdHpiFeatures { 494 EMMC_EXT_CSD_HPI_SUPPORT = (1 << 0), /* HPI mechanism supported flag. */ 495 EMMC_EXT_CSD_HPI_IMPLEMENTATION = (1 << 1), /* 0x0 : HPI mechanism implementation based on CMD13. 496 * 0x1 : HPI mechanism implementation based on CMD12. 497 */ 498 }; 499 500 /* EXT_CSD access modes */ 501 enum EmmcExtCsdAccessMode { 502 EMMC_EXT_CSD_CMD_SET = 0x00, /* The command set is changed according to the Cmd Set field of the argument. */ 503 EMMC_EXT_CSD_SET_BITS = 0x01, /* 504 * The bits in the pointed byte are set, 505 * according to the '1' bits in the Value field. 506 */ 507 EMMC_EXT_CSD_CLEAR_BITS = 0x02, /* 508 * The bits in the pointed byte are cleared, 509 * according to the '1' bits in the Value field. 510 */ 511 EMMC_EXT_CSD_WRITE_BYTE = 0x03, /* The Value field is written into the pointed byte. */ 512 }; 513 514 enum EmmcExtCsdBusWidth { 515 EMMC_EXT_CSD_BUS_WIDTH_1 = 0, /* 1 bit mode */ 516 EMMC_EXT_CSD_BUS_WIDTH_4 = 1, /* 4 bit mode */ 517 EMMC_EXT_CSD_BUS_WIDTH_8 = 2, /* 8 bit mode */ 518 EMMC_EXT_CSD_DDR_BUS_WIDTH_4 = 5, /* 4 bit DDR mode */ 519 EMMC_EXT_CSD_DDR_BUS_WIDTH_8 = 6, /* 8 bit DDR mode */ 520 EMMC_EXT_CSD_BUS_WIDTH_STROBE = (1 << 7), /* Enhanced strobe mode */ 521 }; 522 523 enum EmmcExtCsdBusTiming { 524 EMMC_EXT_CSD_BUS_TIMING_HS = 1, /* High speed */ 525 EMMC_EXT_CSD_BUS_TIMING_HS200 = 2, /* HS200 */ 526 EMMC_EXT_CSD_BUS_TIMING_HS400 = 3, /* HS400 */ 527 EMMC_EXT_CSD_BUS_DRV_STR_SHIFT = 4, /* Driver Strength shift */ 528 }; 529 530 enum EmmcExtCsdCmdSet { 531 EMMC_EXT_CSD_CMD_SET_NORMAL = (1 << 0), 532 EMMC_EXT_CSD_CMD_SET_SECURE = (1 << 1), 533 EMMC_EXT_CSD_CMD_SET_CPSECURE = (1 << 2), 534 }; 535 536 /* 537 * PWR_CL_ff_vvv, PWR_CL_DDR_ff_vvv. 538 * Bits [7:4] code the current consumption for the 8 bit bus configuration. 539 * Bits [3:0] code the current consumption for the 4 bit bus configuration. 540 */ 541 #define EMMC_EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */ 542 #define EMMC_EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */ 543 #define EMMC_EXT_CSD_PWR_CL_8BIT_SHIFT 4 544 #define EMMC_EXT_CSD_PWR_CL_4BIT_SHIFT 0 545 546 /* 547 * S_A_TIMEOUT [217]. 548 * Max register value defined is 0x17 which equals 838.86ms timeout. Values between 0x18 and 0xFF are reserved. 549 */ 550 #define MAX_S_A_TIMEOUT_VALUE 0x17 551 552 /* 553 * PARTITIONING_SUPPORT [160]. 554 * Bit[7:2]: Reserved. 555 * Bit[1]: ENH_ATTRIBUTE_EN. 556 * 0x0: Device can not have enhanced technological features in partitions and user data area. 557 * 0x1: Device can have enhanced technological features in partitions and user data area. 558 * Bit[0]: PARTITIONING_EN. 559 * 0x0: Device does not support partitioning features. 560 * 0x1: Device supports partitioning features. 561 * Partitioning feature is optional for device. 562 */ 563 #define PARTITIONING_SUPPORT_ENH_ATTRIBUTE_EN (1 << 1) 564 #define PARTITIONING_SUPPORT_PARTITIONING_EN (1 << 0) 565 566 /* 567 * PARTITIONS_ATTRIBUTE [156]. 568 * Bit[7:5]: Reserved. 569 * Bit[4]: ENH_4. 0x0: Default; 0x1: Set Enhanced attribute in General Purpose partition 4. 570 * Bit[3]: ENH_3. 0x0: Default; 0x1: Set Enhanced attribute in General Purpose partition 3. 571 * Bit[2]: ENH_2. 0x0: Default; 0x1: Set Enhanced attribute in General Purpose partition 2. 572 * Bit[1]: ENH_1. 0x0: Default; 0x1: Set Enhanced attribute in General Purpose partition 1. 573 * Bit[0]: ENH_USR. 0x0: Default; 0x1: Set Enhanced attribute in User Data Area. 574 */ 575 #define PARTITIONS_ATTRIBUTE_ENH_4 (1 << 4) 576 #define PARTITIONS_ATTRIBUTE_ENH_3 (1 << 3) 577 #define PARTITIONS_ATTRIBUTE_ENH_2 (1 << 2) 578 #define PARTITIONS_ATTRIBUTE_ENH_1 (1 << 1) 579 #define PARTITIONS_ATTRIBUTE_ENH_USR (1 << 0) 580 581 /* 582 * The Extended CSD register defines the card properties and selected modes. It is 512 bytes long. The most 583 * significant 320 bytes are the Properties segment, which defines the card capabilities and cannot be modified 584 * by the host. The lower 192 bytes are the Modes segment, which defines the configuration the card is 585 * working in. These modes can be changed by the host by means of the SWITCH command. 586 */ 587 struct EmmcExtCsd { 588 uint8_t rev; /* EXT_CSD_REV: [192] */ 589 uint8_t eraseGroupDef; /* ERASE_GROUP_DEF: [175] */ 590 uint8_t secFeatureSupport; /* SEC_FEATURE_SUPPORT: [231] */ 591 uint8_t relWrSecorCount; /* Reliable write sector count(REL_WR_SEC_C): [222] */ 592 uint8_t wrRelParam; /* Write reliability parameter register(WR_REL_PARAM): [166] */ 593 uint8_t partConfig; /* PARTITION_CONFIG: [179] */ 594 uint32_t partSwitchTime; /* PARTITION_SWITCH_TIME:[199], ms */ 595 uint32_t saTimeout; /* Sleep/Awake Timeout = 100ns * 2^S_A_timeout, S_A_TIMEOUT: [217], Units: 100ns */ 596 uint32_t hsMaxDtr; /* high-speed max data transfer rate, according to cardType */ 597 uint32_t sectors; /* SEC_COUNT: [215:212], 512B/secter */ 598 uint32_t cardType; /* see rawCardType */ 599 uint32_t hcEraseSize; /* High-capacity erase unit size: [224] */ 600 uint32_t hcEraseTimeout; /* High-capacity erase timeout: [223], ms */ 601 uint32_t secTrimMult; /* Secure TRIM Multiplier: [229] */ 602 uint32_t secEraseMult; /* Secure Erase Multiplier: [230] */ 603 uint32_t trimTimeout; /* TRIM Multiplier: [232], TRIM Timeout = 300ms * TRIM_MULT */ 604 bool enhAreaEnable; /* enable bit */ 605 uint64_t enhAreaOffset; /* Enhanced User Data Start Address(ENH_START_ADDR): [139:136] */ 606 uint32_t enhAreaSize; /* Enhanced User Data Area Size(ENH_SIZE_MULT): [142:140] */ 607 uint32_t cache_size; /* Units: KB */ 608 bool hpiEnable; /* HPI enable bit */ 609 bool hpi; /* HPI_FEATURES: [503], Bit[0]: HPI_SUPPORT */ 610 uint32_t hpiCmd; /* HPI_FEATURES: [503], Bit[1]: HPI_IMPLEMENTATION, cmd used as HPI */ 611 uint32_t dataSectorSize; /* 512 bytes or 4KB */ 612 uint32_t data_tag_unit_size; /* DATA TAG UNIT size */ 613 uint32_t boot_ro_lock; /* ro lock support */ 614 uint32_t bootSize; /* Boot Partition size = 128Kbytes * BOOT_SIZE_MULT, BOOT_SIZE_MULT: [226] */ 615 uint8_t pwrClF52V195; /* Power class for 52MHz at 1.95V: [200] */ 616 uint8_t pwrClF26V195; /* Power class for 26MHz at 1.95V: [201] */ 617 uint8_t pwrClF52V360; /* Power class for 52MHz at 3.6V: [202] */ 618 uint8_t pwrClF26V360; /* Power class for 26MHz at 3.6V: [203] */ 619 uint8_t pwrClF200V195; /* Power class for 200MHz at 1.95V: [236] */ 620 uint8_t pwrClF200V360; /* Power class for 200MHz at 1.95V: [237] */ 621 uint8_t pwrClDdrF52V195; /* Power class for 52MHz, DDR at 3.6V: [238] */ 622 uint8_t pwrClDdrF52V360; /* Power class for 52MHz, DDR at 3.6V: [239] */ 623 uint8_t rawPartitionSupport; /* PARTITIONING_SUPPORT: [160] */ 624 uint8_t rawErasedMemCount; /* ERASED_MEM_CONT: [181] */ 625 uint8_t strobeSupport; /* strobe Support:[184] */ 626 uint8_t rawCsdStructure; /* CSD_STRUCTURE: [194] */ 627 uint8_t rawCardType; /* CARD_TYPE: [196] */ 628 uint8_t outOfInterruptTime; /* OUT_OF_INTERRUPT_TIME: [198], Units: 10ms */ 629 uint8_t rawSaTimeout; /* S_A_TIMEOUT: [217], 100ns */ 630 uint8_t rawHcWpGrpSize; /* High-capacity write protect group size(HC_WP_GRP_SIZE): [221] */ 631 uint8_t rawEraseTimeoutMult; /* ERASE_TIMEOUT_MULT: [223] */ 632 uint8_t rawHcEraseGrpSize; /* HC_ERASE_GRP_SIZE: [224] */ 633 uint8_t rawSecTrimMult; /* SEC_TRIM_MULT: [229] */ 634 uint8_t rawSecEraseMult; /* SEC_ERASE_MULT: [230] */ 635 uint8_t rawSecFeatureSupport; /* SEC_FEATURE_SUPPORT: [231] */ 636 uint8_t rawTrimMult; /* TRIM_MULT: [232] */ 637 uint8_t rawSectors[EMMC_EXT_CSD_SEC_CNT_BYTES]; /* SEC_COUNT: [215:212] */ 638 }; 639 640 /* SD_SWITCH_FUNC mode */ 641 #define SD_SWITCH_FUNC_CHECK 0 642 #define SD_SWITCH_FUNC_SET 1 643 644 /* SD_SWITCH_FUNC function groups */ 645 #define SD_SWITCH_FUNC_GRP_ACCESS 0 646 647 /* SD_SWITCH_FUNC access modes */ 648 #define SD_SWITCH_FUNC_ACCESS_DEF 0 649 #define SD_SWITCH_FUNC_ACCESS_HS 1 650 651 /* 652 * As a response to the switch function command, the SD Memory Card will send R1 response on the CMD line, 653 * and 512 bits of status on the DAT lines. 654 */ 655 #define SD_SWITCH_FUNCTION_STATUS_BYTES_LEN 64 656 657 enum SdCmdCode { 658 SD_CMD_SEND_RELATIVE_ADDR = 3, /* ask the card to publish a new relative address (RCA). */ 659 SD_CMD_SWITCH_FUNC = 6, /* Checks switchable function (mode 0) and switches card function (mode 1). */ 660 SD_CMD_SEND_IF_COND = 8, /* 661 * Sends SD Memory Card interface condition, which includes host supply voltage 662 * information and asks the card whether card supports voltage. 663 */ 664 SD_CMD_SWITCH_VOLTAGE = 11, /* Switch to 1.8V bus signaling level. */ 665 SD_CMD_SEND_TUNING_BLOCK = 19, /* 64 bytes tuning pattern is sent for SDR50 and SDR104. */ 666 SD_CMD_ERASE_WR_BLK_START = 32, /* sets the address of the first writeblock to be erased. */ 667 SD_CMD_ERASE_WR_BLK_END = 33, /* sets the address of the last write block of the continuous range to be erased. */ 668 SD_ACMD_SET_BUS_WIDTH = 6, /* 669 * Defines the data bus width ('00' =1bit or '10' =4 bits bus) to be used for data 670 * transfer. The allowed data bus widths are given in SCR register. 671 */ 672 SD_ACMD_SD_STATUS = 13, /* Send the SD Memory Card status. */ 673 SD_ACMD_SEND_NUM_WR_BLKS = 22, /* Send the number of the written (without errors) write blocks. */ 674 SD_ACMD_OP_COND = 41, /* 675 * Asks the accessed card to send its operating condition register(OCR) content 676 * in the response on the CMD line. 677 */ 678 SD_ACMD_SEND_SCR = 51, /* Reads the SD Configuration Register(SCR). */ 679 }; 680 681 enum SdSwitchFuncMode { 682 SD_SWITCH_FUNC_MODE_CHECK = 0, /* 683 * Check function is used to query if the card supports 684 * a specific function or functions. 685 */ 686 SD_SWITCH_FUNC_MODE_SET = 1, /* Set function is used to switch the functionality of the card. */ 687 }; 688 689 enum SdSwitchFuncGroup { 690 SD_SWITCH_FUNC_GROUP_1 = 0, /* Function Group 1 is defined as Bus Speed Mode switch. */ 691 SD_SWITCH_FUNC_GROUP_2 = 1, /* Function Group 2 is defined for Command System extension. */ 692 SD_SWITCH_FUNC_GROUP_3 = 2, /* Function Group 3 is defined as driver strength selection for UHS-I modes. */ 693 SD_SWITCH_FUNC_GROUP_4 = 3, /* Function Group 4 is defined as current limit switch for each UHS-I mode. */ 694 SD_SWITCH_FUNC_GROUP_5 = 4, /* reserved. */ 695 SD_SWITCH_FUNC_GROUP_6 = 5, /* reserved. */ 696 }; 697 698 struct SdSwitchFuncParam { 699 uint32_t mode; 700 uint32_t group; 701 uint32_t value; 702 }; 703 704 enum SdBusSpeedMode { 705 SD_BUS_SPEED_MODE_DS = 0, /* Default Speed up to 25MHz 3.3V signaling */ 706 SD_BUS_SPEED_MODE_UHS_SDR12 = 0, /* SDR up to 25MHz 1.8V signaling */ 707 SD_BUS_SPEED_MODE_HS = 1, /* High Speed 50MHz 3.3V signaling */ 708 SD_BUS_SPEED_MODE_UHS_SDR25 = 1, /* SDR up to 50MHz 1.8V signaling */ 709 SD_BUS_SPEED_MODE_UHS_SDR50 = 2, /* SDR up to 100MHz 1.8V signaling */ 710 SD_BUS_SPEED_MODE_UHS_SDR104 = 3, /* SDR up to 208MHz 1.8V signaling */ 711 SD_BUS_SPEED_MODE_UHS_DDR50 = 4, /* DDR up to 50MHz 1.8V signaling */ 712 }; 713 714 /* sd max data transfer rate */ 715 enum SdMaxDtr { 716 SD_HIGH_SPEED_MAX_DTR = 50000000, 717 SD_UHS_SDR104_MAX_DTR = 208000000, 718 SD_UHS_SDR50_MAX_DTR = 100000000, 719 SD_UHS_DDR50_MAX_DTR = 50000000, 720 SD_UHS_SDR25_MAX_DTR = 50000000, 721 SD_UHS_SDR12_MAX_DTR = 25000000, 722 }; 723 724 enum SdDrvType { 725 SD_DRV_TYPE_B = 0x01, 726 SD_DRV_TYPE_A = 0x02, 727 SD_DRV_TYPE_C = 0x04, 728 SD_DRV_TYPE_D = 0x08, 729 }; 730 731 enum SdMaxCurrentLimitBit { 732 SD_MAX_CURRENT_LIMIT_200 = (1 << 0), /* 200mA bit */ 733 SD_MAX_CURRENT_LIMIT_400 = (1 << 1), /* 400mA bit */ 734 SD_MAX_CURRENT_LIMIT_600 = (1 << 2), /* 600mA bit */ 735 SD_MAX_CURRENT_LIMIT_800 = (1 << 3), /* 800mA bit */ 736 }; 737 738 enum SdMaxCurrentLimitValue { 739 SD_MAX_CURRENT_LIMIT_200_VALUE = 0, /* 200mA */ 740 SD_MAX_CURRENT_LIMIT_400_VALUE = 1, /* 400mA */ 741 SD_MAX_CURRENT_LIMIT_600_VALUE = 2, /* 600mA */ 742 SD_MAX_CURRENT_LIMIT_800_VALUE = 3, /* 800mA */ 743 }; 744 745 enum SdScrSpec { 746 SD_SCR_SPEC_0 = 0, 747 SD_SCR_SPEC_1 = 1, 748 SD_SCR_SPEC_2 = 2, 749 }; 750 751 enum SdScrBusWidths { 752 SD_SCR_BUS_WIDTHS_1 = (1 << 0), 753 SD_SCR_BUS_WIDTHS_4 = (1 << 2), 754 }; 755 756 #define SD_SCR_SPEED_CLASS_CONTROL_SUPPORT (0x1 << 0) /* cmd20 */ 757 #define SD_SCR_SET_BLOCK_COUNT_SUPPORT (0x1 << 1) /* cmd23 */ 758 759 /* SD Configuration register */ 760 struct SdScr { 761 uint8_t sdSpec; 762 uint8_t sdSpec3; 763 uint8_t sdBusWidths; 764 uint8_t cmdSupport; 765 }; 766 767 /* 768 * SPEED_CLASS Code Field, SEPPD_CLASS : VAL. 769 * 0 : 0, 1 : 2, 2 : 4, 3 : 6, 4 : 10, 5-FF : reversed. 770 */ 771 enum SdSsrSpeedClass { 772 SD_SSR_SPEED_CLASS_0 = 0, 773 SD_SSR_SPEED_CLASS_1 = 1, 774 SD_SSR_SPEED_CLASS_2 = 2, 775 SD_SSR_SPEED_CLASS_3 = 3, 776 SD_SSR_SPEED_CLASS_4 = 4, 777 SD_SSR_SPEED_CLASS_REV = 5, 778 }; 779 780 enum SdSsrSpeedClassVal { 781 SD_SSR_SPEED_CLASS_0_VAL = 0, 782 SD_SSR_SPEED_CLASS_1_VAL = 2, 783 SD_SSR_SPEED_CLASS_2_VAL = 4, 784 SD_SSR_SPEED_CLASS_3_VAL = 6, 785 SD_SSR_SPEED_CLASS_4_VAL = 10, 786 SD_SSR_SPEED_CLASS_REV_VAL = 20, 787 }; 788 789 enum SdSsrUhsSpeedGrade { 790 SD_SSR_UHS_SPEED_GRADE_0 = 0, /* Less than 10MB/sec */ 791 SD_SSR_UHS_SPEED_GRADE_1 = 1, /* 10MB/sec and above */ 792 SD_SSR_UHS_SPEED_GRADE_2 = 2, /* Reversed */ 793 SD_SSR_UHS_SPEED_GRADE_3 = 3, /* 30MB/sec and above */ 794 SD_SSR_UHS_SPEED_GRADE_4 = 4, /* 4h-Fh, Reversed */ 795 }; 796 797 /* SD Status register */ 798 struct SdSsr { 799 uint8_t speedClass; 800 uint8_t auSize; 801 uint16_t eraseSize; 802 uint8_t eraseTimeout; 803 uint8_t eraseOffset; 804 uint8_t uhsSpeedGrade; 805 uint32_t auValue; 806 }; 807 808 union SdSpec3BusMode { 809 uint32_t data; 810 struct dataBits { 811 uint32_t uhsSdr12 : 1; 812 uint32_t uhsSdr25 : 1; 813 uint32_t uhsSdr50 : 1; 814 uint32_t uhsSdr104 : 1; 815 uint32_t uhsDdr50 : 1; 816 817 uint32_t reserved : 27; 818 } bits; 819 }; 820 821 struct SdSwitchCaps { 822 enum SdMaxDtr hsMaxDtr; 823 enum SdMaxDtr uhsMaxDtr; 824 union SdSpec3BusMode sdSpec3BusMode; 825 enum SdDrvType sdSpec3DrvType; 826 enum SdMaxCurrentLimitBit sdSpec3CurrLimit; 827 }; 828 829 enum SdioCmdCode { 830 /* 831 * It is similar to the operation of ACMD41 for SD memory cards. 832 * It is used to inquire about the valtage range needed by the I/O card. 833 */ 834 SDIO_SEND_OP_COND = 5, 835 /* 836 * It is the simplest means to access a single register within the total 128K of register space in any I/O function, 837 * including the common I/O area (CIA). This command reads or writes 1 byte using only 1 command/response pair. 838 * A common use is to initialize registers or monitor status values for I/O functions. This command is the fastest 839 * means to read or write single I/O registers, as it requires only a single command/response pair. 840 */ 841 SDIO_RW_DIRECT = 52, 842 /* 843 * This command allows the reading or writing of a large number of I/O registers with a single command. 844 * Since this is a data transfer command, it provides the highest possible transfer rate. 845 */ 846 SDIO_RW_EXTENDED = 53, 847 }; 848 849 /* Card Common Control Registers (CCCR), Register Name--Address. */ 850 enum SdioCccrAddr { 851 CCCR_SDIO_REVISION = 0x00, /* bit3-bit0: CCCR_REVISION, bit7-bit4: SDIO_REVISION. */ 852 SD_SPECIFICATION_REVISION = 0x01, /* bit3-bit0: SD_REVISION, bit7-bit4: RFU. */ 853 IO_ENABLE = 0x02, /* bit7-bit1: IOEx, bit0: RFU. */ 854 IO_READY = 0x03, /* bit7-bit1: IORx, bit0: RFU. */ 855 INT_ENABLE = 0x04, /* bit7-bit1: IENx, bit0: IENM. */ 856 INT_PENDING = 0x05, /* bit7-bit1: INTx, bit0: RFU. */ 857 IO_ABORT = 0x06, /* bit2-bit0: ASx, bit3: RES, bit7-bit4: RFU. */ 858 BUS_INTERFACE_CONTROL = 0x07, /* 859 * bit1-bit0: Bus Width, bit2: S8B, bit3: RFU, bit4:RFU, bit5: ECSI, 860 * bit6: SCSI, bit7: CD Disable. 861 */ 862 CARD_CAPBILITY = 0x08, /* 863 * bit0: SDC, bit1: SMB, bit2: SRW, bit3: SBS, bit4: S4MI, bit5: E4MI, 864 * bit6: LSC, bit7: 4BLS. 865 */ 866 COMMON_CIS_POINTER = 0x09, /* 09h-0Bh, Pointer to card's common CIS. */ 867 BUS_SUSPEND = 0x0C, /* bit0: BS, bit1: BR, bit7-bit2: RFU. */ 868 FUNCTION_SELECT = 0x0D, /* bit3-bit0: FSx, bit6-bit4: RFU, bit7: DF. */ 869 EXEC_FLAG = 0x0E, /* bit7-bit0: EXx. */ 870 FN0_BLOCK_SIZE = 0x10, /* 11h-10h, I/O block size for Function 0. */ 871 POWER_CONTROL = 0x12, /* bit0: SMPC, bit1: EMPC, bit7-bit2: RFU. */ 872 BUS_SPEED_SELECT = 0x13, /* bit0: SHS, bit3-bit1: BSSx, bit7-bit4: RFU. */ 873 UHS_I_SUPPORT = 0x14, /* bit0: SSDR50, bit1: SSDR104, bit2: SDDR50, bit7-bit3: RFU. */ 874 DRIVER_STRENGTH = 0x15, /* bit0: SDTA, bit1: SDTC, bit2: SDTD, bit3: RFU, bit4: DTS0, bit5: DTS1, bit7-6: RFU. */ 875 INTERRUPT_EXTENSION = 0x16, /* bit0: SAI, bit1: EAI, bit7-bit2: RFU. */ 876 }; 877 878 /* CCCR_SDIO_REVISION-->bit3-bit0: CCCR_REVISION. */ 879 enum SdioCccrRev { 880 SDIO_CCCR_VERSION_1_00 = 0x00, /* CCCR/FBR Version 1.00 */ 881 SDIO_CCCR_VERSION_1_10 = 0x01, /* CCCR/FBR Version 1.10 */ 882 SDIO_CCCR_VERSION_1_20 = 0x02, /* CCCR/FBR Version 1.20 */ 883 SDIO_CCCR_VERSION_3_00 = 0x03, /* CCCR/FBR Version 3.00 */ 884 }; 885 886 /* CCCR_SDIO_REVISION-->bit7-bit4: SDIO_REVISION. */ 887 enum SdioCccrSdioRev { 888 SDIO_CCCR_SDIO_REV_1_00 = 0x00, /* SDIO Spec Version 1.00 */ 889 SDIO_CCCR_SDIO_REV_1_10 = 0x01, /* SDIO Spec Version 1.10 */ 890 SDIO_CCCR_SDIO_REV_1_20 = 0x02, /* SDIO Spec Version 1.20 */ 891 SDIO_CCCR_SDIO_REV_2_00 = 0x03, /* SDIO Spec Version 2.00 */ 892 SDIO_CCCR_SDIO_REV_3_00 = 0x04, /* SDIO Spec Version 3.00 */ 893 }; 894 895 /* SD_SPECIFICATION_REVISION-->bit3-bit0: SD_REVISION. */ 896 enum SdioCccrSdRev { 897 SDIO_CCCR_SD_REV_1_01 = 0x00, /* SD Physical Spec Version 1.01 */ 898 SDIO_CCCR_SD_REV_1_10 = 0x01, /* SD Physical Spec Version 1.10 */ 899 SDIO_CCCR_SD_REV_2_00 = 0x02, /* SD Physical Spec Version 2.00 */ 900 SDIO_CCCR_SD_REV_3_0X = 0x03, /* SD Physical Spev Version 3.0X */ 901 }; 902 903 /* IO_ABORT-->bit3: RES(I/O Card Reset). 904 * Setting the RES to 1 shall cause I/O functions perform a soft reset. This does not affect the current card 905 * protocol selection and CD Disable. It is auto cleared, so there is no need to rewrite a value of 0. 906 */ 907 #define SDIO_CCCR_RES 0x08 908 909 /* BUS_INTERFACE_CONTROL-->bit1-bit0: Bus Width. */ 910 enum SdioCccrWidth { 911 SDIO_CCCR_WIDTH_1BIT = 0x00, /* 1-bit */ 912 SDIO_CCCR_WIDTH_4BIT = 0x02, /* 4-bit bus */ 913 SDIO_CCCR_WIDTH_8BIT = 0x03 /* 8-bit bus(only for embedded SDIO) */ 914 }; 915 916 /* BUS_INTERFACE_CONTROL-->bit5: ECSI. Enable Continuous SPI Interrupt. */ 917 #define SDIO_CCCR_ECSI 0x20 918 /* BUS_INTERFACE_CONTROL-->bit6: SCSI. Support Continuous SPI Interrupt. */ 919 #define SDIO_CCCR_SCSI 0x40 920 /* 921 * BUS_INTERFACE_CONTROL-->bit7: CD Disable. Card Detect Disable. 922 * Connect[0]/DisConnect[1] the 10K-90K ohm pull-up resistor on CD/DAT[3](pin1) of the card. 923 * The pull-up may be used for card detection. This bit shall be set to 1 before issuing CMD53. 924 */ 925 #define SDIO_CCCR_CD_DISABLE 0x80 926 927 /* CARD_CAPBILITY */ 928 enum SdioCccrCapbility { 929 SDIO_CCCR_CAP_SDC = 0x01, /* Support Direct Command(CMD52). If set, all functions shall accept and execute 930 * the CMD52 while data transfer is underway on the DAT[x] lines. 931 */ 932 SDIO_CCCR_CAP_SMB = 0x02, /* Support Multiple Block Transfer. If set, all functions shall accept and execute 933 * CMD53 with the optional block mode bit set. 934 */ 935 SDIO_CCCR_CAP_SRW = 0x04, /* Support Read Wait. If set, all functions on the card are able to accept 936 * the wait signal on DAT[2]. 937 */ 938 SDIO_CCCR_CAP_SBS = 0x08, /* Support Bus Control. If set, all functions except 0 shall accept a request to 939 * suspend operations and resume under host control. 940 */ 941 SDIO_CCCR_CAP_S4MI = 0x10, /* Support Block Gap Interrupt. Support bit of interrupt between blocks of data 942 * in 4-bit SD mode. If set, the SDIO card is able to signal an interrupt between 943 * blocks while data transfer is in progress. 944 */ 945 SDIO_CCCR_CAP_E4MI = 0x20, /* Enable Block Gap Interrupt. If set, the card shall generate interrupts 946 * during 4 bit multi-block data transfer. 947 */ 948 SDIO_CCCR_CAP_LSC = 0x40, /* Low-Speed Card. If set, it indicates that the SDIO card is a Low-Speed Card. 949 * if this bit is clear, The SDIO card is Full-Speed card. 950 */ 951 SDIO_CCCR_CAP_4BLS = 0x80, /* 4-bit Mode Support for Low-Speed Card. if the SDIO card is a Low-Speed Card and 952 * it supports 4-bit data transfer, then this bit shall be set. 953 */ 954 }; 955 956 /* POWER_CONTROL-->bit0: SMPC, bit1: EMPC */ 957 enum SdioCccrPower { 958 SDIO_CCCR_POWER_SMPC = 0x01, /* Support Power Control. */ 959 SDIO_CCCR_POWER_EMPC = 0x02, /* Enable Power Control. */ 960 }; 961 962 /* BUS_SPEED_SELECT-->bit0: SHS. Support High-Speed. */ 963 #define SDIO_CCCR_BUS_SPEED_SHS 0x01 964 /* 965 * BUS_SPEED_SELECT-->BSS0. BSS0 = 0, Default Speed(25MHz); BSS0 = 1, High Speed(50MHz). 966 * If the card is initialized 3.3V signaling, then BSS0 is effective. When SHS is set to 0, 967 * writing to this bit is ignored and always indicates 0. The card operates in High-Speed timing mode 968 * with a clock rate up to 50MHz. 969 */ 970 #define SDIO_CCCR_BUS_SPEED_EHS 0x02 971 972 /* 973 * BUS_SPEED_SELECT-->bit3-bit1: BSSx. 974 * If the card is initialized 1.8V signaling, then BSS[2:0] is effective. A card that supports UHS-I shall 975 * support High Speed mode and SHS shall be set to 1. 976 */ 977 enum SdioCccrBusSpeed { 978 SDIO_CCCR_BUS_SPEED_SDR12 = 0, /* Max Clock Freq: 25MHz. */ 979 SDIO_CCCR_BUS_SPEED_SDR25 = 1, /* Max Clock Freq: 50MHz. */ 980 SDIO_CCCR_BUS_SPEED_SDR50 = 2, /* Max Clock Freq: 100MHz. */ 981 SDIO_CCCR_BUS_SPEED_SDR104 = 3, /* Max Clock Freq: 208MHz. */ 982 SDIO_CCCR_BUS_SPEED_DDR50 = 4, /* Max Clock Freq: 50MHz. */ 983 }; 984 985 /* UHS_I_SUPPORT-->bit0: SSDR50, bit1: SSDR104, bit2: SDDR50. */ 986 enum SdioCccrUhsISupport { 987 SDIO_CCCR_UHS_I_SSDR50 = (1 << 0), /* Support SDR50. If this bit set to 1, SDR12 and SDR25 shall be supported. */ 988 SDIO_CCCR_UHS_I_SSDR104 = (1 << 1), /* 989 * Support SDR104. If this bit set to 1, 990 * SDR12, SDR25 and SDR50 shall be supported. 991 */ 992 SDIO_CCCR_UHS_I_SDDR50 = (1 << 2), /* 993 * Support DDR50. If this bit set to 1, 994 * SDR12, SDR25 and SDR50 shall be supported. 995 */ 996 }; 997 998 /* DRIVER_STRENGTH-->bit0: SDTA, bit1: SDTC, bit2: SDTD, bit3: RFU, bit4: DTS0, bit5: DTS1, bit7-bit6: RFU. */ 999 enum SdioCccrDriveTypeSupport { 1000 SDIO_CCCR_DRIVE_SDTA = (1 << 0), 1001 SDIO_CCCR_DRIVE_SDTC = (1 << 1), 1002 SDIO_CCCR_DRIVE_SDTD = (1 << 2), 1003 }; 1004 1005 /* DRIVER_STRENGTH-->bit4: DTS0, bit5: DTS1. */ 1006 enum SdioCccrDriveTypeSelect { 1007 SDIO_CCCR_DTS_TYPE_B = (0 << 4), 1008 SDIO_CCCR_DTS_TYPE_A = (1 << 4), 1009 SDIO_CCCR_DTS_YPE_C = (2 << 4), 1010 SDIO_CCCR_DTS_TYPE_D = (3 << 4), 1011 }; 1012 1013 /* INTERRUPT_EXTENSION-->bit0: SAI, bit1: EAI. */ 1014 #define SDIO_CCCR_SAI 0x01 /* Support Asynchronous Interrupt. */ 1015 #define SDIO_CCCR_EAI 0x02 /* Enable Asynchronous Interrupt. */ 1016 1017 /* Function Basic Registers (FBR), Register Name--Address. */ 1018 enum SdioFbrAddr { 1019 SDIO_FBR_STD_FUNCTION_INTERFACE_CODE = 0x00, /* 1020 * bit7: CSA enable, bit6: support CSA, bit5-bit4L: RFU, 1021 * bit3-bit0: Standard SDIO Function Interface Code. 1022 */ 1023 SDIO_FBR_EXT_STD_FUNCTION_INTERFACE_CODE = 0x01, /* Extended Standard SDIO Function Interface Code. */ 1024 SDIO_FBR_POWER_SELECTION = 0x02, /* bit0: SPS, bit1: EPS, bit3-bit2: RFU, bit7-bit4: PSx. */ 1025 SDIO_FBR_POINTER_CIS = 0x09, /* n09h-n0Bh: (Card Information Structure)CIS pointer */ 1026 SDIO_FBR_POINTER_CSA = 0x0C, /* n0Ch-n0Eh: (Code Storage Area)CSA pointer */ 1027 SDIO_FBR_CSA_DATA_ACCESS = 0x0F, /* Data access window to CSA. */ 1028 SDIO_FBR_IO_BLOCK_SIZE = 0x10, /* I/O block size. */ 1029 }; 1030 1031 /* The address of FBR is from 00n00h to 00nFFh where n is the function number(1 to 7). */ 1032 #define SDIO_FBR_BASE_ADDR(f) ((f) * 0x100) 1033 1034 /* SDIO_FBR_STD_FUNCTION_INTERFACE_CODE-->bit3-bit0: Standard SDIO Function Interface Code. */ 1035 enum SdioFbrStdFuncIfCode { 1036 SDIO_FBR_NO_STD_IF = 0x00, /* No SDIO standard interface supported by this function. */ 1037 SDIO_FBR_STD_UART = 0x01, /* This function support SDIO standard UART. */ 1038 SDIO_FBR_STD_BLUETOOTH_TYPE_A = 0x02, /* This function support SDIO Bluetooth Type-A standard interface. */ 1039 SDIO_FBR_STD_BLUETOOTH_TYPE_B = 0x03, /* This function support SDIO Bluetooth Type-B standard interface. */ 1040 SDIO_FBR_STD_GPS = 0x04, /* This function support SDIO GPS standard interface. */ 1041 SDIO_FBR_STD_CAMERA = 0x05, /* This function support SDIO Camera standard interface. */ 1042 SDIO_FBR_STD_PHS = 0x06, /* This function support SDIO PHS standard interface. */ 1043 SDIO_FBR_STD_WLAN = 0x07, /* This function support SDIO WLAN interface. */ 1044 SDIO_FBR_STD_EMBEDDED_SDIO_ATA = 0x08, /* This function support Embedded SDIO-ATA standard interface. */ 1045 SDIO_FBR_STD_BLUETOOTH_TYPE_A_AMP = 0x09, /* This function support SDIO Bluetooth Type-A AMP standard interface. */ 1046 SDIO_FBR_STD_SDIO_IF = 0x0F, /* 1047 * This function support an SDIO standard interface number greater than Eh. 1048 * In this case, the value in SDIO_FBR_EXT_STD_FUNCTION_INTERFACE_CODE identifies 1049 * the standard SDIO interfaces type. 1050 */ 1051 }; 1052 1053 /* SDIO_FBR_STD_FUNCTION_INTERFACE_CODE-->bit6: support CSA. */ 1054 #define SDIO_FBR_SUPPORTS_CSA 0x40 1055 /* 1056 * SDIO_FBR_STD_FUNCTION_INTERFACE_CODE-->bit7: CSA enable. 1057 * If this function does not support CSA, then this bit shall be R/O and always read as 0. 1058 */ 1059 #define SDIO_FBR_CSA_ENABLE 0x80 1060 1061 /* 1062 * SDIO_FBR_POWER_SELECTION-->bit0: SPS(Support Power Selection). 1063 * SPS = 0: This function has no Power Selection. EPS shall be zero. 1064 * SPS = 1: This function has 2 Power modes which are selected by EPS. 1065 * This bit is effective when EMPC = 1 in CCCR and PS[3:0] = 0. 1066 */ 1067 #define SDIO_FBR_POWER_SPS 0x01 1068 /* 1069 * SDIO_FBR_POWER_SELECTION-->bit1: EPS(Enable Power Selection). 1070 * Enable (low) Power Selection. 1071 */ 1072 #define SDIO_FBR_POWER_EPS 0x02 1073 /* Sdio function 1-7. */ 1074 #define SDIO_MAX_FUNCTION_NUMBER 7 1075 1076 /* SDIO CMD5 response R4, [24]S18A(Switching to 1.8V Accepted). */ 1077 #define SDIO_R4_S18A (1 << 24) 1078 /* R4, [27]Memory Present. Set to 1 if the card also contains SD memory. Set to 0 if the card is I/O only. */ 1079 #define SDIO_R4_MEMORY_PRESENT (1 << 27) 1080 1081 /* R5: [15:8]Response flags, indicating the status of the SDIO card. */ 1082 enum SdioR5CardStatusBits { 1083 SDIO_R5_COM_CRC_ERROR = (1 << 15), /* The CRC chack of the previous command failed. */ 1084 SDIO_R5_ILLEGAL_COMMAND = (1 << 14), /* Command not legal for the card State. */ 1085 SDIO_R5_ERROR = (1 << 11), /* A general or an unknuwn error occurred during the operation. */ 1086 SDIO_R5_FUNCTION_NUMBER = (1 << 9), /* An invalid function number was requested. */ 1087 SDIO_R5_OUT_OF_RANGE = (1 << 8), /* The command's argument was out of the allowed range for this card. */ 1088 }; 1089 1090 /* R5: [13:12]IO_CURRENT_STATE. */ 1091 enum SdioCurrentState { 1092 SDIO_CURRENT_STATE_DIS = 0, /* Disable. Initialize, Standby and Inactive States(card not selected). */ 1093 SDIO_CURRENT_STATE_CMD = 1, /* DAT lines free. Command waiting, Executing CMD52 in CMD State. */ 1094 SDIO_CURRENT_STATE_TRN = 2, /* Transfer. Command executing with data transfer using DAT[0] or DAT[3:0] lines. */ 1095 }; 1096 1097 /* Card Common Control Registers(CCCR). */ 1098 struct SdioCccr { 1099 uint32_t sdioRev; 1100 uint32_t sdRev; 1101 uint32_t multiBlock : 1; 1102 uint32_t lowSpeed : 1; 1103 uint32_t lowSpeed4Bit : 1; 1104 uint32_t highPower : 1; 1105 uint32_t highSpeed : 1; 1106 uint32_t disableCd : 1; 1107 }; 1108 1109 /* 1110 * n09-n0B, these three bytes make up a 24-bit pointer(only the lower 17 bits are used) to the start of the 1111 * Card Information Structure(CIS) that is associated with each function. 1112 */ 1113 #define SDIO_CCCR_CIS_START_ADDR_BYTES 3 1114 1115 /* 1116 * There are 2 tuples with only a tuple code, the CISTPL_NULL and the CISTPL_END. These tuples do not have any 1117 * additional bytes. For all other tuples, bytes 1 of each tuple contains a link to the next tuple in the chain. 1118 * If the link field is 0, the the tuple body is empty. 1119 * If the link contains FFh, the this tuple is the last tuple in its chain. 1120 */ 1121 enum SdioCisTupleCode { 1122 SDIO_CIS_TPL_NULL = 0x00, /* Null tuple. */ 1123 SDIO_CIS_TPL_CHECKSUM = 0x10, /* Checksum Control. */ 1124 SDIO_CIS_TPL_VERS_1 = 0x15, /* Level 1 version/product-information. */ 1125 SDIO_CIS_TPL_ALTSTR = 0x16, /* The Alternate Language String Tuple. */ 1126 SDIO_CIS_TPL_MANFID = 0x20, /* Manufacturer Identification String Tuple. */ 1127 SDIO_CIS_TPL_FUNCID = 0x21, /* Function Identification Tuple. */ 1128 SDIO_CIS_TPL_FUNCE = 0x22, /* Function Extensions. */ 1129 SDIO_CIS_TPL_SDIO_STD = 0x91, /* Additional information for functions built to support application 1130 * specifications for standard SDIO functions. 1131 */ 1132 SDIO_CIS_TPL_SDIO_EXT = 0x92, /* Reserved for future use with SDIO devices. */ 1133 SDIO_CIS_TPL_END = 0xFF, /* The End-0f-chain Tuple. */ 1134 }; 1135 1136 #define SDIO_CIS_TPL_MANFID_MIN_SIZE 0x04 1137 #define SDIO_CIS_TPL_FUNCE_COMMON_MIN_SIZE 0x04 1138 #define SDIO_CIS_TPL_FUNCE_FUNCTION_PC_MIN_SIZE 0x1C 1139 #define SDIO_CIS_TPL_FUNCE_FUNCTION_PC_MAX_SIZE 0x2A 1140 #define SDIO_CIS_TPLFE_ENABLE_TIMEOUT_VAL_DEF 100 1141 1142 enum SdioCisTupleFunceType { 1143 SDIO_CIS_TPL_FUNCE_COMMON = 0, /* This tuple gives the host common information about the card. */ 1144 SDIO_CIS_TPL_FUNCE_FUNCTION_PC = 1, /* Extended Data 01h is defined for Power Control. */ 1145 SDIO_CIS_TPL_FUNCE_FUNCTION_PS = 2, /* Extended of this tuple indicates that the card supports the Power State. */ 1146 }; 1147 1148 /* Card Information Structure(CIS). */ 1149 struct SdioCis { 1150 uint16_t vendorId; 1151 uint16_t deviceId; 1152 uint16_t blkSize; 1153 uint32_t maxDtr; 1154 }; 1155 1156 /* 1157 * The Card Information Structure is one or more chains(or linked lists) of data blocks or tuples. 1158 * Basic Tuple Format: TPL_CODE, TPL_LINK, The tuple body. 1159 */ 1160 struct SdioCisTuple { 1161 uint8_t tplCode; /* Tuple code: CISTPL_XXX */ 1162 uint8_t tplLink; /* TPL_LINK Offset to next tuple in chains. This is the number of bytes in the tuple body. */ 1163 uint8_t tplBody[0]; /* The tuple body(n bytes). */ 1164 }; 1165 1166 struct SdioCmdParam { 1167 uint32_t funcNum; 1168 uint32_t regAddr; 1169 uint8_t writeData; 1170 bool incrAddrFlag; 1171 bool writeflag; 1172 bool scatterFlag; 1173 uint32_t scatterLen; 1174 }; 1175 1176 struct SdioRwBlockInfo { 1177 uint32_t addr; 1178 uint8_t *buf; 1179 uint32_t size; 1180 uint32_t scatterLen; 1181 bool writeFlag; 1182 bool incrAddrFlag; 1183 bool scatterFlag; 1184 }; 1185 1186 #ifdef __cplusplus 1187 #if __cplusplus 1188 } 1189 #endif 1190 #endif /* __cplusplus */ 1191 1192 #endif /* _MMC_PROTOCOL_H */ 1193